This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.

A wideband noise-cancelling receiver front-end is proposed in this brief. As a basic architecture, a low-noise transconductance amplifier, a passive mixer, and a transimpedance amplifier are employed to compose the wideband receiver. To achieve wideband input matching for the transconductor, a global feedback method is adopted. Since the wideband receiver has to minimize linearity degradation if a large blocker signal exists out-of-band, a linearization technique is applied for the transconductor circuit. The linearization cancels third-order intermodulation distortion components and increases linearity; however, the additional circuits used in linearization generate excessive noise. A noise-cancelling architecture that employs an auxiliary path cancels noise signals generated in the main path. The designed receiver front-end is fabricated using a 65-nm CMOS process. The receiver operates in the frequency range of 25 MHz-2 GHz with a gain of 49.7 dB. The in-band input-referred third-order intercept point is improved by 12.3 dB when the linearization is activated, demonstrating the effectiveness of the linearization technique.

This Paper presents the design of a wideband variable gain amplifier (VGA) using 0.18 µm standard CMOS technology. The proposed VGA realizes wideband flat gain using wideband flat negative capacitance. It achieves a 3 dB gain bandwidth of 1 GHz with a maximum gain of 23 dB. Also, it shows P1 dB of -33 to -6 dBm over the gain range of -28 to 23 dB. The overall current consumption is 5.5 mA under a 1.5 V supply.

In this Letter, a dumbbell-shaped patch loaded slotline(PLS) is proposed. Like the conventional defected ground structure(DGS) for a microstrip line, we show that the proposed PLS can provide a wide bandstop characteristic in some frequency bands with only one or small number of unit cells. Also, the equivalent circuit model for a unit section is derived from the analysis of the field distributions in the structure and its circuit parameters are determined by means of full wave numerical simulations. This equivalent circuit is shown to be dual to that of the typical DGS in a microstrip line. A broadband microstrip to slotline transition is incorporated in the PLS in order to measure the characteristics of the structure. The experimental results agree well with the simulations and show the validity of the modeling for the proposed PLS.

We present a seven-bit multilayer true-time delay (TTD) circuit operating from 1 to 7GHz for wideband phased array antennas. By stacking advanced substrates with low dielectric loss, the TTD with PCB process is miniaturized and has low insertion loss. The signal vias with surrounding ground vias are designed to provide impedance matching throughout the band, allowing the overall group delay to be flat. The standard deviation of the TTD for all states is below 19ps, which is 1.87% of the maximum group delay. The maximum delay is 1016ps with resolution of 8ps. The implemented TTD is 36.6×19.4mm2 and consumes 0.65mW at 3.3V supply for all the delay states. The measured input/output return loss is better than 12.1dB for the band of 1-7GHz.

In this paper, a waveguide-fed slot-coupled microstrip antenna is proposed as enhanced feeding structure of microstrip antenna and an analysis is pesented. The presence of dielectric substrate between a strip and a slot is explicitly taken into account in this analysis. The evaluation of the antenna characteristics is carried out using the method of moments and the spectral domain approach in terms of the electric current distribution on the strip and the magnetic current distribution on the slot.

This paper presents a design of a monolithic transformer using bond wires. The proposed transformer structure has several advantages such as high power handling and high efficiency. It shows that the measured insertion loss at the 1.9 GHz range is -1.54 dB (70%), which is higher than the spiral transformer of the same size. Also, it shows a phase error of less than 1 degree.

This paper describes the performance improvement of power amplifiers by defected ground structure (DGS). Due to the excellent capability of harmonic rejection and tuning, DGS plays a great role in improving the major nonlinear behaviors of power amplifier such as output power, harmonics, power added efficiency (PAE), and the ratio between the carrier and the third order intermodulation distortion (C/IMD3). In order to verify the improvement of performances by DGS, measured data for a power amplifier, which adopts a 30 Watts LDMOS device for the operation at 2.1-2.2 GHz, are illustrated under several operating bias currents for two cases, i.e., with and without DGS attached. The principle of the improvement is described by the simple Volterra nonlinear transfer functions with the consideration of different operating classes. The obtained improvement of the 30 Watts power amplifier, under 400 mA of IdsQ as an example, includes the reduction in the second and third harmonics by 17 dB and 20 dB, and the increase in output power, PAE, and C/IMD3 by 1.3 Watts, 3.4%, and 4.7 dB, respectively.

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.

This paper presents the design of a CMOS RF Power Detector (PD) using 0.18 µm standard CMOS technology. The PD is an improved unbalanced source coupled pair incorporating an output differential amplifier and sink current steering. It realizes an input detectable power range of -30 to -20 dBm over 0.1-1 GHz. Also it shows a maximum data rate of 30 Mbps with 2 pF output loading under OOK modulation. The overall current consumption is 1.9 mA under a 1.5 V supply.

This paper presents a circuit that improves supply noise rejection using an active inductor circuit. Compared to the conventional designs, the proposed supply noise suppression circuit has better characteristics such as low current consumption and small die size with noise rejection. The circuit was fabricated using 0.13 µm UMC CMOS technology. The experimental results showed that the supply noise was suppressed by 61% with only an increase in size of 20.0 µm 2.5 µm, and the current consumption was under 2 mA.

In this paper, a 24GHz transformer-coupled VCO is presented for a wide linear tuning range in the 0.13-µm CMOS process. The measured results of the proposed VCO show that the center frequency is 23.5GHz with 7.4% frequency tuning range. The output frequency curve has wide linear tuning region (5.5%) at the middle of the curve. Also, the VCO exhibits good phase noise of -110.23dBc/Hz at an offset frequency of 1 MHz. It has a compact chip size of 430 × 500µm2. The VCO core DC power consumption is 5.4mW at 1.35V VDD.

This letter proposes a wideband compact DC block design technique. This DC block has a wide pass-band and wide stop-band and transforms termination impedances. It comprises a pair of coupled lines on a defected ground structure (DGS) with capacitor loading. A periodic DGS pattern increases coupling, and, consequently, a wideband DC block design is allowed with a microstrip process on a high dielectric low height substrate. A DC block with equal termination impedances of 50,$Omega$ and another that transforms 50 into 30,$Omega$ are fabricated. The measured fractional bandwidths are 48% and 47%. The size of the DC block is 16.8$ imes$ 15,mm$^2(0.057lambda_0 imes 0.051lambda_0)$.

This paper proposes a high clutter-rejection technique for wall-penetrating frequency-modulated continuous-wave (FMCW) radar. FMCW radars are widely used, as they moderate the receiver saturation problem in wall-penetrating applications by attenuating short-range clutter such as wall-clutter. However, conventional FMCW radars require a very high-order high-pass filter (HPF) to attenuate short-range clutter. A delay-line (DL) is exploited to overcome this problem. Time-delay shifts beat frequencies formed by reflection waves. This means that a proper time-delay increases the ratio of target-beat frequency to clutter-beat frequency. Consequently, low-order HPF fully attenuates short-range clutter. A third-order HPF rejects more than 20 dB and 30 dB for clutter located at 6 m and 3 m, respectively, with a target located at 9 m detection with a 10,000 GHz/s chirp rate and a 28 ns delay-line.

This paper proposes a multiway power divider for wideband (4:1) beamforming arrays. The divider's input reflection characteristic (S11) is achieved using a multisection stepped-impedance transformer. Moreover, the divider's isolation (S32) bandwidth is increased by incorporating inductors and capacitors in addition to the conventional resistor only isolation networks of the divider. The analysis of the proposed divider and comparison with the previous research model was conducted with four-way configuration. A prototype of a wideband eight-way power divider is fabricated and measured. The measured fractional bandwidth is about 137% from 1.3 to 6.8GHz with the -10dB criteria of input reflection (S11), output reflection (S22) and isolation (S32) simultaneously.

This paper presents a design optimization method for a Gm-C active filter via geometric programming (GP). We first describe a GP-compatible model of a cascaded Gm-C filter that forms a biquadratic output transfer function. The bias, gain, bandwidth, and signal-to-noise ratio (SNR) of the Gm-C filter are described in a GP-compatible way. To further enhance the accuracy of the model, two modeling techniques are introduced. The first, a two-step selection method, chooses whether a saturation or subthreshold model should be used for each transistor in the filter to enhance the modeling accuracy. The second, a bisection method, is applied to include non-posynomial inequalities in the filter modeling. The presented filter model is optimized via a GP solver along with proposed modeling techniques. The numerical experiments over wide ranges of design specifications show good agreement between model and simulation results, with the average error for gain, bandwidth, and SNR being less than 9.9%, 4.4%, and 14.6%, respectively.

This paper describes the design method of a broadband CMOS stacked power amplifier using harmonic control over wide bandwidths in a 0.11,$mu $m standard CMOS process. The high-efficiency can be obtained over wide bandwidths by designing a load impedance circuit as purely reactive as possible to the harmonics with broadband fundamental matching, which is based on continuous Class-F mode of operation. Furthermore, the stacked topology overcomes the low breakdown voltage limit of CMOS transistor and increases output impedance. With a 5-V supply and a fixed matching circuitry, the suggested power amplifier (PA) achieves a saturated output power of over 26.7,dBm and a drain efficiency of over 38% from 1.6,GHz to 2.2,GHz. In W-CDMA modulation signal measurements, the PA generates linear power and power added efficiency of over 23.5,dBm and 33% (@ACLR $=-33$,dBc).

A reconfigurable broadband linear power amplifier (PA) for long-range WLAN applications fabricated in a 180nm RF CMOS process is presented here. The proposed reconfigurable in/output matching network provides the PA with broadband capability at the two center frequencies of 0.5GHz and 0.85GHz. The output matching network is realized by a switchable transformer which shows maximum peak passive efficiencies of 65.03% and 73.45% at 0.45GHz and 0.725GHz, respectively. With continuous wave sources, a 1-dB bandwidth (BW1-dB) according to saturated output power is 0.4-1.2GHz, where it shows a minimum output power with a power added efficiency (PAE) of 25.62dBm at 19.65%. Using an adaptive power cell configuration at the common gate transistor, the measured PA under LTE 16-QAM 20MHz (40MHz) signals shows an average output power with a PAE exceeding 20.22 (20.15) dBm with 7.42 (7.35)% at an ACLRE-UTRA of -30dBc, within the BW1-dB.

A new method is proposed for determining the parasitic extrinsic resistances of MESFETs and HEMTs from the measured S-parameters under active bias. The proposed method is based on the fact that the difference between drain resistance (Rd) and source resistance (Rs) can be found from the measured S-parameters under zero bias condition. It is possible to define the new internal device including intrinsic device and three extrinsic resistances by eliminating the parasitic imaginary terms. Three resistances can be calculated easily via the presented explicit three equations, which are induced from the fact that 1) the real parts of Yint,11 and Yint,12 of intrinsic Y-parameters are very small or almost zero, 2) the transformation relations between S-, Z-, and Y-matrices. The modelled S-parameters calculated by the obtained resistances and all the other equivalent circuit parameters are in good agreement with the measured S-parameters up to 40 GHz.