IEICE TRANSACTIONS on Electronics
A Simplified Broadband Output Matching Technique for CMOS stacked Power Amplifiers
Summary :
This paper describes the design method of a broadband CMOS stacked power amplifier using harmonic control over wide bandwidths in a 0.11 μm standard CMOS process. The high-efficiency can be obtained over wide bandwidths by designing a load impedance circuit as purely reactive as possible to the harmonics with broadband fundamental matching, which is based on continuous Class-F mode of operation. Furthermore, the stacked topology overcomes the low breakdown voltage limit of CMOS transistor and increases output impedance. With a 5-V supply and a fixed matching circuitry, the suggested power amplifier (PA) achieves a saturated output power of over 26.7 dBm and a drain efficiency of over 38% from 1.6 GHz to 2.2 GHz. In W-CDMA modulation signal measurements, the PA generates linear power and power added efficiency of over 23.5 dBm and 33% (@ACLR =-33 dBc).
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E97-C No.10 pp.938-940
- Publication Date
- 2014/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E97.C.938
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
Jaeyong KO
SNU
Kihyun KIM
SNU
Jaehoon SONG
SNU
Sangwook NAM
SNU
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Jaeyong KO, Kihyun KIM, Jaehoon SONG, Sangwook NAM, "A Simplified Broadband Output Matching Technique for \ CMOS stacked Power Amplifiers" in IEICE TRANSACTIONS on Electronics,
vol. E97-C, no. 10, pp. 938-940, October 2014, doi: 10.1587/transele.E97.C.938.
Abstract: This paper describes the design method of a broadband CMOS stacked power amplifier using harmonic control over wide bandwidths in a 0.11 μm standard CMOS process. The high-efficiency can be obtained over wide bandwidths by designing a load impedance circuit as purely reactive as possible to the harmonics with broadband fundamental matching, which is based on continuous Class-F mode of operation. Furthermore, the stacked topology overcomes the low breakdown voltage limit of CMOS transistor and increases output impedance. With a 5-V supply and a fixed matching circuitry, the suggested power amplifier (PA) achieves a saturated output power of over 26.7 dBm and a drain efficiency of over 38% from 1.6 GHz to 2.2 GHz. In W-CDMA modulation signal measurements, the PA generates linear power and power added efficiency of over 23.5 dBm and 33% (@ACLR =-33 dBc).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.938/_p
Copy
@ARTICLE{e97-c_10_938,
author={Jaeyong KO, Kihyun KIM, Jaehoon SONG, Sangwook NAM, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Simplified Broadband Output Matching Technique for \ CMOS stacked Power Amplifiers},
year={2014},
volume={E97-C},
number={10},
pages={938-940},
abstract={This paper describes the design method of a broadband CMOS stacked power amplifier using harmonic control over wide bandwidths in a 0.11 μm standard CMOS process. The high-efficiency can be obtained over wide bandwidths by designing a load impedance circuit as purely reactive as possible to the harmonics with broadband fundamental matching, which is based on continuous Class-F mode of operation. Furthermore, the stacked topology overcomes the low breakdown voltage limit of CMOS transistor and increases output impedance. With a 5-V supply and a fixed matching circuitry, the suggested power amplifier (PA) achieves a saturated output power of over 26.7 dBm and a drain efficiency of over 38% from 1.6 GHz to 2.2 GHz. In W-CDMA modulation signal measurements, the PA generates linear power and power added efficiency of over 23.5 dBm and 33% (@ACLR =-33 dBc).},
keywords={},
doi={10.1587/transele.E97.C.938},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - A Simplified Broadband Output Matching Technique for \ CMOS stacked Power Amplifiers
T2 - IEICE TRANSACTIONS on Electronics
SP - 938
EP - 940
AU - Jaeyong KO
AU - Kihyun KIM
AU - Jaehoon SONG
AU - Sangwook NAM
PY - 2014
DO - 10.1587/transele.E97.C.938
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2014
AB - This paper describes the design method of a broadband CMOS stacked power amplifier using harmonic control over wide bandwidths in a 0.11 μm standard CMOS process. The high-efficiency can be obtained over wide bandwidths by designing a load impedance circuit as purely reactive as possible to the harmonics with broadband fundamental matching, which is based on continuous Class-F mode of operation. Furthermore, the stacked topology overcomes the low breakdown voltage limit of CMOS transistor and increases output impedance. With a 5-V supply and a fixed matching circuitry, the suggested power amplifier (PA) achieves a saturated output power of over 26.7 dBm and a drain efficiency of over 38% from 1.6 GHz to 2.2 GHz. In W-CDMA modulation signal measurements, the PA generates linear power and power added efficiency of over 23.5 dBm and 33% (@ACLR =-33 dBc).
ER -
English
