This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.

This Paper presents the design of a wideband variable gain amplifier (VGA) using 0.18 µm standard CMOS technology. The proposed VGA realizes wideband flat gain using wideband flat negative capacitance. It achieves a 3 dB gain bandwidth of 1 GHz with a maximum gain of 23 dB. Also, it shows P1 dB of -33 to -6 dBm over the gain range of -28 to 23 dB. The overall current consumption is 5.5 mA under a 1.5 V supply.

This paper presents a design of a monolithic transformer using bond wires. The proposed transformer structure has several advantages such as high power handling and high efficiency. It shows that the measured insertion loss at the 1.9 GHz range is -1.54 dB (70%), which is higher than the spiral transformer of the same size. Also, it shows a phase error of less than 1 degree.

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.

This paper presents a circuit that improves supply noise rejection using an active inductor circuit. Compared to the conventional designs, the proposed supply noise suppression circuit has better characteristics such as low current consumption and small die size with noise rejection. The circuit was fabricated using 0.13 µm UMC CMOS technology. The experimental results showed that the supply noise was suppressed by 61% with only an increase in size of 20.0 µm 2.5 µm, and the current consumption was under 2 mA.