A 2.3-7 GHz CMOS High Gain LNA Using CS-CS Cascode with Coupling C
Summary :
A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.8 pp.1091-1094
- Publication Date
- 2009/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1091
- Type of Manuscript
- BRIEF PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Hangue PARK, Sungho LEE, Jaejun LEE, Sangwook NAM, "A 2.3-7 GHz CMOS High Gain LNA Using CS-CS Cascode with Coupling C" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 8, pp. 1091-1094, August 2009, doi: 10.1587/transele.E92.C.1091.
Abstract: A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1091/_p
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@ARTICLE{e92-c_8_1091,
author={Hangue PARK, Sungho LEE, Jaejun LEE, Sangwook NAM, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 2.3-7 GHz CMOS High Gain LNA Using CS-CS Cascode with Coupling C},
year={2009},
volume={E92-C},
number={8},
pages={1091-1094},
abstract={A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.},
keywords={},
doi={10.1587/transele.E92.C.1091},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - A 2.3-7 GHz CMOS High Gain LNA Using CS-CS Cascode with Coupling C
T2 - IEICE TRANSACTIONS on Electronics
SP - 1091
EP - 1094
AU - Hangue PARK
AU - Sungho LEE
AU - Jaejun LEE
AU - Sangwook NAM
PY - 2009
DO - 10.1587/transele.E92.C.1091
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2009
AB - A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.
ER -
English
