IEICE TRANSACTIONS on Electronics
High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches
Summary :
This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E92-C No.12 pp.1548-1550
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E92.C.1548
- Type of Manuscript
- LETTER
- Category
- Electronic Circuits
Authors
Keyword
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Jaejun LEE, Sungho LEE, Yonghoon SONG, Sangwook NAM, "High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 12, pp. 1548-1550, December 2009, doi: 10.1587/transele.E92.C.1548.
Abstract: This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1548/_p
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@ARTICLE{e92-c_12_1548,
author={Jaejun LEE, Sungho LEE, Yonghoon SONG, Sangwook NAM, },
journal={IEICE TRANSACTIONS on Electronics},
title={High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches},
year={2009},
volume={E92-C},
number={12},
pages={1548-1550},
abstract={This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.},
keywords={},
doi={10.1587/transele.E92.C.1548},
ISSN={1745-1353},
month={December},}
Copy
TY - JOUR
TI - High Gain and Wide Range Time Amplifier Using Inverter Delay Chain in SR Latches
T2 - IEICE TRANSACTIONS on Electronics
SP - 1548
EP - 1550
AU - Jaejun LEE
AU - Sungho LEE
AU - Yonghoon SONG
AU - Sangwook NAM
PY - 2009
DO - 10.1587/transele.E92.C.1548
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2009
AB - This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 µm standard CMOS technology and the experimental results agree well with the theory.
ER -
English
