We present a seven-bit multilayer true-time delay (TTD) circuit operating from 1 to 7GHz for wideband phased array antennas. By stacking advanced substrates with low dielectric loss, the TTD with PCB process is miniaturized and has low insertion loss. The signal vias with surrounding ground vias are designed to provide impedance matching throughout the band, allowing the overall group delay to be flat. The standard deviation of the TTD for all states is below 19ps, which is 1.87% of the maximum group delay. The maximum delay is 1016ps with resolution of 8ps. The implemented TTD is 36.6×19.4mm2 and consumes 0.65mW at 3.3V supply for all the delay states. The measured input/output return loss is better than 12.1dB for the band of 1-7GHz.

This paper proposes a multiway power divider for wideband (4:1) beamforming arrays. The divider's input reflection characteristic (S11) is achieved using a multisection stepped-impedance transformer. Moreover, the divider's isolation (S32) bandwidth is increased by incorporating inductors and capacitors in addition to the conventional resistor only isolation networks of the divider. The analysis of the proposed divider and comparison with the previous research model was conducted with four-way configuration. A prototype of a wideband eight-way power divider is fabricated and measured. The measured fractional bandwidth is about 137% from 1.3 to 6.8GHz with the -10dB criteria of input reflection (S11), output reflection (S22) and isolation (S32) simultaneously.

This paper presents a design optimization method for a Gm-C active filter via geometric programming (GP). We first describe a GP-compatible model of a cascaded Gm-C filter that forms a biquadratic output transfer function. The bias, gain, bandwidth, and signal-to-noise ratio (SNR) of the Gm-C filter are described in a GP-compatible way. To further enhance the accuracy of the model, two modeling techniques are introduced. The first, a two-step selection method, chooses whether a saturation or subthreshold model should be used for each transistor in the filter to enhance the modeling accuracy. The second, a bisection method, is applied to include non-posynomial inequalities in the filter modeling. The presented filter model is optimized via a GP solver along with proposed modeling techniques. The numerical experiments over wide ranges of design specifications show good agreement between model and simulation results, with the average error for gain, bandwidth, and SNR being less than 9.9%, 4.4%, and 14.6%, respectively.