The use of intelligent agents is on the rise, fueled by the unprecedented growth in the Internet and web based applications. Consequently, agent-oriented software is becoming large and complex. To support a systematic development of such software, an agent-oriented software development methodology is necessary. This paper focuses on the modeling phase of agent-oriented software life cycle and, presents an approach for agent modeling consisting of Agent Elicitation, Intra, and Inter Agent modeling methods. Agent Elicitation deals with identifying and extracting agents from "classes" in the real world. Intra Agent Modeling involves expressing agent characteristics - Goal, Belief, Plan and Capability - whereas, Inter Agent modeling incorporates agent mobility and communication in a multi-agent system.

This paper presents a design optimization method for a Gm-C active filter via geometric programming (GP). We first describe a GP-compatible model of a cascaded Gm-C filter that forms a biquadratic output transfer function. The bias, gain, bandwidth, and signal-to-noise ratio (SNR) of the Gm-C filter are described in a GP-compatible way. To further enhance the accuracy of the model, two modeling techniques are introduced. The first, a two-step selection method, chooses whether a saturation or subthreshold model should be used for each transistor in the filter to enhance the modeling accuracy. The second, a bisection method, is applied to include non-posynomial inequalities in the filter modeling. The presented filter model is optimized via a GP solver along with proposed modeling techniques. The numerical experiments over wide ranges of design specifications show good agreement between model and simulation results, with the average error for gain, bandwidth, and SNR being less than 9.9%, 4.4%, and 14.6%, respectively.

This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.