This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.

In this paper, a wide input range CMOS multi-mode active rectifier is presented for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the mode of the multi-mode rectifier is automatically selected by switches among the original rectifier mode, 1-stage voltage multiplier mode, and 2-stage voltage multiplier mode. In the original rectifier, the range of the rectified output DC voltage is from 9 V to 19 V for an input AC voltage from 10 V to 20 V. In the multi-mode rectifier, the input-range is wider compared to the original rectifier by 5 V. As a result, the rectified output DC voltage ranges from 7.5 V to 19 V for an input AC voltage from 5 V to 20 V. The proposed multi-mode rectifier is fabricated in a 0.35 µm CMOS process with an active area of around 2500 µm 1750 µm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency is about 94%.

We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.