Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs
Summary :
This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E100-C No.5 pp.504-512
- Publication Date
- 2017/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E100.C.504
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Soyeon JOO
Sungkyunkwan University
Jintae KIM
Konkuk University
SoYoung KIM
Sungkyunkwan University
Keyword
Latest Issue
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Soyeon JOO, Jintae KIM, SoYoung KIM, "Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 5, pp. 504-512, May 2017, doi: 10.1587/transele.E100.C.504.
Abstract: This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.504/_p
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@ARTICLE{e100-c_5_504,
author={Soyeon JOO, Jintae KIM, SoYoung KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs},
year={2017},
volume={E100-C},
number={5},
pages={504-512},
abstract={This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.},
keywords={},
doi={10.1587/transele.E100.C.504},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs
T2 - IEICE TRANSACTIONS on Electronics
SP - 504
EP - 512
AU - Soyeon JOO
AU - Jintae KIM
AU - SoYoung KIM
PY - 2017
DO - 10.1587/transele.E100.C.504
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2017
AB - This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 µm CMOS process are consistent with the design guidelines suggested in this work.
ER -
English
