This paper presents a wide range DCO with fine discrete tuning steps using a ΣΔ modulation technique for UWB frequency synthesizer. The proposed discrete tuning scheme provides a low effective frequency resolution without any degradation of the phase noise performance. With its three step discrete tunings, the DCO simultaneously has a wide tuning range and fine tuning steps. The frequency synthesizer was implemented using 0.13 µm CMOS technology. The tuning range of the DCO is 5.8-6.8 GHz with an effective frequency resolution of 3.9 kHz. It achieves a measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range of 16.8% with the power consumption of 5.9 mW. The figure of merit with the tuning range is -181.5 dBc/Hz.

This paper presents a wide frequency range delay-locked loop implemented with a 0.35 µm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.

A simple phase detector reducing the pattern dependent jitter in clock recovery circuit is developed in this paper. The developed phase detector automatically aligns the recovered to clock in the center of the data eye, while producing no ripple to the control voltage in locked condition of the PLL based clock recovery circuit. The UP and DOWN signals are separately generated to align them in locked condition. Thus, no explicit transient waveforms do not exist at the output of the phase detector. The elimination of high frequency ripple improves the jitter characteristics of the clock recovery circuit. The delay unit used in our phase detector requires no accurate control of the delay time. This feature eliminates the use of DLL to generate the precise delay time, which reduce the power consumption and area of the phase detector. The simulation shows that the RMS timing jitter is reduced by more than four times when compared with the conventional scheme. The rms jitter is 32 ps for the proposed phase detector and 133 ps for the phase detector in conventional scheme. In conventional scheme, even when the lock is achieved, the phase detector produces a triwave transient on the control voltage of the VCO, which depends on the data pattern. In the proposed phase detector, no such transient waveforms do not exist. The proposed phase detector can be incorporated in high performance clock recovery circuit for data communication systems.

In this paper, we propose a two-step TDC with phase-interpolator and time amplifier to satisfy high resolution at 2.4 GHz input frequency by implementing delay time less than that of an inverter delay. The accuracy of phase-interpolator is improved for process variation using the resistor automatic-tuning circuit. The gain of time amplifier is improved using the delay time difference between two delay cells. It is implemented in a 0.13 µm CMOS process with a die area of 0.68 mm2. And the power consumption is 14.4 mW at a 1.2 V supply voltage. The resolution and input frequency of the TDC are 0.357 ps and 2.4 GHz, respectively.

This paper presents a baseband filter for multi-mode applications with a new automatic tuning method. 5th-order Chebyshev low pass filter is designed for implementing the baseband channel-select filter. Capacitors and resistors were shared between modes to minimize the area. The new corner frequency tuning method is proposed to compensate the process variation. This method can reduce the noise level due to MOS switches.

In this paper, a wide input range CMOS multi-mode active rectifier is presented for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the mode of the multi-mode rectifier is automatically selected by switches among the original rectifier mode, 1-stage voltage multiplier mode, and 2-stage voltage multiplier mode. In the original rectifier, the range of the rectified output DC voltage is from 9 V to 19 V for an input AC voltage from 10 V to 20 V. In the multi-mode rectifier, the input-range is wider compared to the original rectifier by 5 V. As a result, the rectified output DC voltage ranges from 7.5 V to 19 V for an input AC voltage from 5 V to 20 V. The proposed multi-mode rectifier is fabricated in a 0.35 µm CMOS process with an active area of around 2500 µm 1750 µm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency is about 94%.

A class-E power amplifier (PA) with novel dynamic biasing scheme is proposed to enhance power added efficiency (PAE) over a wide power range. A look-up table (LUT) adjusts input power and drain supply voltage simultaneously to keep switch mode condition of a power transistor and to optimize the PAE. Experimental results show that the class-E PA using the proposed scheme with harmonic suppression filter gives the PAE higher than 80% over 8.5,dB range with less than 40,dBc harmonic suppression.

This paper presents a wide tuning range VCO with an automatic frequency, gain, and two-step amplitude calibration loop for Digital TV (DTV) tuner applications. To cover the wide tuning range, the fully digital automatic frequency calibration (AFC) loop is used. In addition to the AFC loop, a two-step negative-Gm tuning loop is proposed to provide the optimum negative-Gm to the LC tank in a wide frequency range with a fine resolution. In the coarse negative-Gm tuning loop, the number of active negative-Gm cells is selected digitally based on the target frequency. In the fine negative-Gm tuning loop, the negative-Gm is tuned finely with the bias voltage of the VCO. Also, the digital VCO gain calibration scheme is proposed to compensate for the gain variation in a wide tuning range. The VCO tuning range is 2.6 GHz, from 1.7 GHz to 4.3 GHz, and the power consumption is 2 mA to 4 mA from a 1.8 V supply. The measured VCO phase noise is -120 dBc/Hz at 1 MHz offset.

This paper investigates limitations of adjacent channel power ratio (ACPR) improvement in predistortion (pre-D) linearizer used with nonlinear RF power amplifiers (PAs) when the PA model is not perfectly acquired in pre-D design. The error between the physical PA and the nonlinear model is expanded by pre-D function and its power spectral density (PSD) works as limitations in ACPR improvement of the pre-D linearizer. An analytical estimation of ACPR limitations in RF PAs driven by digitally modulated input signal is derived using a formulation of autocorrelation function. The analysis technique is validated with the example of the memory polynomial PA model with the quasi-memoryless pre-D linearizer. The technique is also verified by comparing predicted ACPR limitation with measured limitation for a RF PA with 802.11g input signal.

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within 10 µs. It is implemented in a 0.18 µm CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8nV/ input referred noise, and 5-dBm IIP3 at 60-mW power consumption. The power detector shows the 35 dB dynamic range for 100 MHz input.

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. To change the bandwidth, the charge pump current and the loop filter zero resistor should be changed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 µs and the phase noise is -121 dBc/ at 600 kHz offset. This chip is fabricated with 0.25 µm CMOS technology, and the die area is 0.7 mm2.1mm. The power consumption is 54 mW at 2.7 V supply voltage.