IEICE TRANSACTIONS on Electronics
A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique
Summary :
This paper presents a wide frequency range delay-locked loop implemented with a 0.35 µm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.9 pp.1900-1902
- Publication Date
- 2005/09/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.9.1900
- Type of Manuscript
- LETTER
- Category
- Integrated Electronics
Authors
Keyword
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Kang-Yoon LEE, "A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 9, pp. 1900-1902, September 2005, doi: 10.1093/ietele/e88-c.9.1900.
Abstract: This paper presents a wide frequency range delay-locked loop implemented with a 0.35 µm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.9.1900/_p
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@ARTICLE{e88-c_9_1900,
author={Kang-Yoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique},
year={2005},
volume={E88-C},
number={9},
pages={1900-1902},
abstract={This paper presents a wide frequency range delay-locked loop implemented with a 0.35 µm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.},
keywords={},
doi={10.1093/ietele/e88-c.9.1900},
ISSN={},
month={September},}
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TY - JOUR
TI - A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 1900
EP - 1902
AU - Kang-Yoon LEE
PY - 2005
DO - 10.1093/ietele/e88-c.9.1900
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2005
AB - This paper presents a wide frequency range delay-locked loop implemented with a 0.35 µm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.
ER -
English
