Timing vernier (i.e., digital-to-time converter) is a key component of the pin-electronics circuit board installed in automated digital-VLSI test equipment, and it is used to create fine delays of less than one-cycle time of a clock signal. This paper presents a new on-the-fly (timing-) jitter suppression technique which makes it possible to use low-power plain-CMOS-logic-based timing verniers. Using a power-compensation line installed at the poststage of the digitally variable delay line, we make every pulse (used as a timing signal) consume a fixed amount of electric energy independent of the required delay amount. Since the power load of intrapowerlines is kept constantly, the jitter increase in the situation of changing the required delay amount on the fly is suppressed. On the basis of the concept, a 10-ns span, 125-MHz timing-vernier macro was designed and fabricated with a CMOS process for logic VLSIs. Every macro installed in a real-time timing-signal generator VLSI achieved the required timing resolution of 31.25ps with a linearity error within 15ps. The on-the-fly jitter was successfully suppressed to a random jitter level (<26ps p-p).

A fully-integrated double-channel 5-Gb/s/ch 2:1 serializer array is designed and fabricated in a standard 0.18-$mu $m CMOS technology, which can be easily expanded to any even-number-channel array, e.g. 12 channels, by means of arrangement in a parallel manner. Besides two conventional half-rate 2:1 serializers, both phase-locked loop and delay-locked loop techniques are employed locally to deal with the involved clocking-related issues, which make the serializer array self-contained, compact and automatic. The system architecture, circuit and layout designs are discussed and analyzed in detail. The chip occupies a die area of 673,$mu $m$, imes ,$667,$mu $m with a core width of only 450,$mu $m. Measurement results show that it works properly without a need for additional clock channels, reference clocks, off-chip tuning, external components, and so on. From a single supply of 1.8,V, a power of 200,mW is consumed and a single-ended swing of above 300,mV for each channel is achieved.

In this paper, newly-found properties of the pseudo-ternary maximum-length shift register sequences (pseudo-ternary M-sequences) are described. In particular, the balance properties, the run-length distribution, the cross-correlation properties, and the decimation relationships are shown. The pseudo-ternary M-sequence is obtained by subtracting the one-chip shifted version from the {+1,-1}-valued M-sequence. Moreover, in this paper, performances of the direct sequence spread spectrum (DS/SS) system using the pseudo-ternary M-sequence are analyzed. In the performance evaluation, tracking error performance (jitter) and bit error rate (BER) performance that takes the jitter into account in DS/SS system with a pseudo-ternary M-sequence non-coherent DLL are evaluated. Using the pseudo-ternary M-sequence instead of the conventional M-sequences can improve the tracking error performance about 2.8 [dB]. Moreover, BER of the DS/SS system using the pseudo-ternary M-sequence is superior about 0.8 [dB] to that using the {+1,-1}-valued M-sequence.

A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-µm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm2.

A new delay-locked loop (DLL)-based multiphase generator is presented. To achieve an arbitrary integer multiplication factor, a voltage-controlled variable delay ring (VCDR) is adopted, and a new "generate and reset" (GNR) cell is developed. The whole circuit of the closed loop was designed and characterized in a 1.2-V 0.13-µm CMOS process. The simulated results show that the loop operates from 1.0 MHz to 1.2 GHz under the supply voltage of 1.2 V, and the GNR cell exhibits low supply sensitivity of 1300-ps/V.

Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N-1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.41.4 mm2 in a 0.18-µm CMOS process and consumes 52 mW.

A false lock free delay-locked loop(DLL) achieving a wide frequency operation and a fine timing resolution is presented. A novel false lock detection technique is proposed to solve the trade-off between a wide frequency range and false locks. This technique enables a fine timing resolution even at a high frequency. In addition, the duty cycle of the input clock is not required to be 50%. This technique is applied to the DLLs in analog front-end LSIs of digital camera systems, with a range of 465 MHz (16) and a timing resolution of 9(40 stages).

This paper presents a wide frequency range delay-locked loop implemented with a 0.35 µm CMOS technology, which can overcome the limited frequency range and false lock problem of conventional delay-locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consumes 19.8 mW and shows 13 ps rms jitter at 3.3 V, 150 MHz condition.

This work describes a 2.4 GHz frequency synthesizer based on a delay-locked loop (DLL). Because the proposed frequency synthesizer is basically developed from a DLL, it has no jitter accumulation thereby resulting in a low close-in phase noise of -105 dBc/Hz. Although only 9 delay cells are used, the proposed delay cell reusing scheme realizes frequency multiplication factors greater than 240 and provides multiple frequency output with the resolution of phase detector (PD) comparison frequency. This architecture has been verified by implementing the synthesizer in a 0.18 µm CMOS technology.

This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.

Pilot symbol-assisted coherent delay-locked code tracking loop (PSA-CDLL) is proposed for DS-CDMA mobile radio. PSA-CDLL applies pilot symbol-assisted coherent channel estimation and uses only the in-phase component of the despread signal for controlling the received spreading code timing. The impact of the multiple access interference (MAI) and background noise can be decreased by about 3 dB compared to non-coherent DLL. The performance of the proposed PSA-CDLL is evaluated by computer simulation. Computer simulation results show that it can significantly reduce the rms tracking jitter of regenerated spreading code replica, thereby improving the bit error rate (BER) performance in fading environments.