IEICE TRANSACTIONS on Electronics
A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges
Summary :
This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.2 pp.220-228
- Publication Date
- 2001/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
- Category
Authors
Koichiro MINAMI
Masayuki MIZUNO
Hiroshi YAMAGUCHI
Toshihiko NAKANO
Yusuke MATSUSHIMA
Yoshikazu SUMI
Takanori SATO
Hisashi YAMASHIDA
Masakazu YAMASHINA
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Koichiro MINAMI, Masayuki MIZUNO, Hiroshi YAMAGUCHI, Toshihiko NAKANO, Yusuke MATSUSHIMA, Yoshikazu SUMI, Takanori SATO, Hisashi YAMASHIDA, Masakazu YAMASHINA, "A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 220-228, February 2001, doi: .
Abstract: This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_220/_p
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@ARTICLE{e84-c_2_220,
author={Koichiro MINAMI, Masayuki MIZUNO, Hiroshi YAMAGUCHI, Toshihiko NAKANO, Yusuke MATSUSHIMA, Yoshikazu SUMI, Takanori SATO, Hisashi YAMASHIDA, Masakazu YAMASHINA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges},
year={2001},
volume={E84-C},
number={2},
pages={220-228},
abstract={This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges
T2 - IEICE TRANSACTIONS on Electronics
SP - 220
EP - 228
AU - Koichiro MINAMI
AU - Masayuki MIZUNO
AU - Hiroshi YAMAGUCHI
AU - Toshihiko NAKANO
AU - Yusuke MATSUSHIMA
AU - Yoshikazu SUMI
AU - Takanori SATO
AU - Hisashi YAMASHIDA
AU - Masakazu YAMASHINA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.
ER -
English
