A microwave variable delay line using a membrane impregnated with liquid crystal was newly fabricated. By employing the membrane impregnated with liquid crystal to the liquid crystal layer of the delay line, the phase-shift response becomes fast independently of the liquid crystal thickness. Experimental results show that the phase-shift response time of 33 ms, which is two orders of magnitude faster than that of a conventional one, is obtained. The new delay line also exhibits a 270-degree phase-shift and non-dispersive delay characteristics over a wide microwave-frequency range, although a higher control voltage is needed. It is also clarified that the phase-shift characteristics to the control voltage depend on the pore size of the membrane. This membrane impregnated with liquid crystal also enables us to make the variable delay line thin and flexible.

This paper describes a 1-GHz portable digital delay-locked loop (DLL) with 0.15-µm CMOS technology. There are three factors contributing to jitter in digital DLLs. One is supply-noise induced jitter, another is jitter caused by delay time resolution and phase step in the delay line, and the third is jitter caused by the sensitivity of the phase detector. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. These techniques were used to fabricate a digital DLL with improved jitter performance. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/ mV supply sensitivity.

This paper describes a low-skew clock distribution technique for multiple targets. An automatic skew compensation circuit, that detects the round-trip delay through a pair of matched interconnection lines and corrects the delay of the variable delay lines, maintains clock skew and delay from among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 900 ps is automatically reduced to 30 ps at a clock frequency of up to 250 MHz with 60 ps of clock jitter. Moreover, they show that the initial clock delay of 1500 ps is cancelled and 60 ps of clock delay can be achieved. The power dissipation is 100 mW at 250 MHz.