Design of a Compact Double-Channel 5-Gb/s/ch Serializer Array for High-Speed Parallel Links
Summary :
A fully-integrated double-channel 5-Gb/s/ch 2:1 serializer array is designed and fabricated in a standard 0.18-μm CMOS technology, which can be easily expanded to any even-number-channel array, e.g. 12 channels, by means of arrangement in a parallel manner. Besides two conventional half-rate 2:1 serializers, both phase-locked loop and delay-locked loop techniques are employed locally to deal with the involved clocking-related issues, which make the serializer array self-contained, compact and automatic. The system architecture, circuit and layout designs are discussed and analyzed in detail. The chip occupies a die area of 673 μm×667 μm with a core width of only 450 μm. Measurement results show that it works properly without a need for additional clock channels, reference clocks, off-chip tuning, external components, and so on. From a single supply of 1.8 V, a power of 200 mW is consumed and a single-ended swing of above 300 mV for each channel is achieved.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E97-C No.11 pp.1104-1111
- Publication Date
- 2014/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E97.C.1104
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Chang-chun ZHANG
Nanjing University of Posts and Telecommunications
Long MIAO
Institute of RF- and OE-ICs, Southeast University
Kui-ying YIN
Nanjing University of Posts and Telecommunications
Yu-feng GUO
Nanjing University of Posts and Telecommunications
Lei-lei LIU
Nanjing University of Posts and Telecommunications
Keyword
Latest Issue
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Chang-chun ZHANG, Long MIAO, Kui-ying YIN, Yu-feng GUO, Lei-lei LIU, "Design of a Compact Double-Channel 5-Gb/s/ch Serializer Array for High-Speed Parallel Links" in IEICE TRANSACTIONS on Electronics,
vol. E97-C, no. 11, pp. 1104-1111, November 2014, doi: 10.1587/transele.E97.C.1104.
Abstract: A fully-integrated double-channel 5-Gb/s/ch 2:1 serializer array is designed and fabricated in a standard 0.18-μm CMOS technology, which can be easily expanded to any even-number-channel array, e.g. 12 channels, by means of arrangement in a parallel manner. Besides two conventional half-rate 2:1 serializers, both phase-locked loop and delay-locked loop techniques are employed locally to deal with the involved clocking-related issues, which make the serializer array self-contained, compact and automatic. The system architecture, circuit and layout designs are discussed and analyzed in detail. The chip occupies a die area of 673 μm×667 μm with a core width of only 450 μm. Measurement results show that it works properly without a need for additional clock channels, reference clocks, off-chip tuning, external components, and so on. From a single supply of 1.8 V, a power of 200 mW is consumed and a single-ended swing of above 300 mV for each channel is achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.1104/_p
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@ARTICLE{e97-c_11_1104,
author={Chang-chun ZHANG, Long MIAO, Kui-ying YIN, Yu-feng GUO, Lei-lei LIU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Compact Double-Channel 5-Gb/s/ch Serializer Array for High-Speed Parallel Links},
year={2014},
volume={E97-C},
number={11},
pages={1104-1111},
abstract={A fully-integrated double-channel 5-Gb/s/ch 2:1 serializer array is designed and fabricated in a standard 0.18-μm CMOS technology, which can be easily expanded to any even-number-channel array, e.g. 12 channels, by means of arrangement in a parallel manner. Besides two conventional half-rate 2:1 serializers, both phase-locked loop and delay-locked loop techniques are employed locally to deal with the involved clocking-related issues, which make the serializer array self-contained, compact and automatic. The system architecture, circuit and layout designs are discussed and analyzed in detail. The chip occupies a die area of 673 μm×667 μm with a core width of only 450 μm. Measurement results show that it works properly without a need for additional clock channels, reference clocks, off-chip tuning, external components, and so on. From a single supply of 1.8 V, a power of 200 mW is consumed and a single-ended swing of above 300 mV for each channel is achieved.},
keywords={},
doi={10.1587/transele.E97.C.1104},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - Design of a Compact Double-Channel 5-Gb/s/ch Serializer Array for High-Speed Parallel Links
T2 - IEICE TRANSACTIONS on Electronics
SP - 1104
EP - 1111
AU - Chang-chun ZHANG
AU - Long MIAO
AU - Kui-ying YIN
AU - Yu-feng GUO
AU - Lei-lei LIU
PY - 2014
DO - 10.1587/transele.E97.C.1104
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2014
AB - A fully-integrated double-channel 5-Gb/s/ch 2:1 serializer array is designed and fabricated in a standard 0.18-μm CMOS technology, which can be easily expanded to any even-number-channel array, e.g. 12 channels, by means of arrangement in a parallel manner. Besides two conventional half-rate 2:1 serializers, both phase-locked loop and delay-locked loop techniques are employed locally to deal with the involved clocking-related issues, which make the serializer array self-contained, compact and automatic. The system architecture, circuit and layout designs are discussed and analyzed in detail. The chip occupies a die area of 673 μm×667 μm with a core width of only 450 μm. Measurement results show that it works properly without a need for additional clock channels, reference clocks, off-chip tuning, external components, and so on. From a single supply of 1.8 V, a power of 200 mW is consumed and a single-ended swing of above 300 mV for each channel is achieved.
ER -
English
