This paper describes a CMOS serial ling allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 µm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Efficient charge recovery logic(ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder(CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-µm CMOS technology with a reduced threshold voltage of 0.2 V.

A simple phase detector reducing the pattern dependent jitter in clock recovery circuit is developed in this paper. The developed phase detector automatically aligns the recovered to clock in the center of the data eye, while producing no ripple to the control voltage in locked condition of the PLL based clock recovery circuit. The UP and DOWN signals are separately generated to align them in locked condition. Thus, no explicit transient waveforms do not exist at the output of the phase detector. The elimination of high frequency ripple improves the jitter characteristics of the clock recovery circuit. The delay unit used in our phase detector requires no accurate control of the delay time. This feature eliminates the use of DLL to generate the precise delay time, which reduce the power consumption and area of the phase detector. The simulation shows that the RMS timing jitter is reduced by more than four times when compared with the conventional scheme. The rms jitter is 32 ps for the proposed phase detector and 133 ps for the phase detector in conventional scheme. In conventional scheme, even when the lock is achieved, the phase detector produces a triwave transient on the control voltage of the VCO, which depends on the data pattern. In the proposed phase detector, no such transient waveforms do not exist. The proposed phase detector can be incorporated in high performance clock recovery circuit for data communication systems.

This paper presents a baseband filter for multi-mode applications with a new automatic tuning method. 5th-order Chebyshev low pass filter is designed for implementing the baseband channel-select filter. Capacitors and resistors were shared between modes to minimize the area. The new corner frequency tuning method is proposed to compensate the process variation. This method can reduce the noise level due to MOS switches.