A CMOS Serial Link for Fully Duplexed Data Communication

Kyeongho LEE; Sungjoon KIM; Gijung AHN; Deog-Kyoon JEONG

A CMOS Serial Link for Fully Duplexed Data Communication

Kyeongho LEE, Sungjoon KIM, Gijung AHN, Deog-Kyoon JEONG

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This paper describes a CMOS serial ling allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 µm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.601-612

Publication Date: 1995/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))

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Kyeongho LEE
Sungjoon KIM
Gijung AHN
Deog-Kyoon JEONG

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Kyeongho LEE, Sungjoon KIM, Gijung AHN, Deog-Kyoon JEONG, "A CMOS Serial Link for Fully Duplexed Data Communication" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 6, pp. 601-612, June 1995, doi: .
Abstract: This paper describes a CMOS serial ling allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 µm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_6_601/_p

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@ARTICLE{e78-c_6_601,
author={Kyeongho LEE, Sungjoon KIM, Gijung AHN, Deog-Kyoon JEONG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A CMOS Serial Link for Fully Duplexed Data Communication},
year={1995},
volume={E78-C},
number={6},
pages={601-612},
abstract={This paper describes a CMOS serial ling allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 µm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A CMOS Serial Link for Fully Duplexed Data Communication
T2 - IEICE TRANSACTIONS on Electronics
SP - 601
EP - 612
AU - Kyeongho LEE
AU - Sungjoon KIM
AU - Gijung AHN
AU - Deog-Kyoon JEONG
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1995
AB - This paper describes a CMOS serial ling allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 µm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.
ER -