An Efficient Charge Recovery Logic Circuit
Summary :
Efficient charge recovery logic(ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder(CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-µm CMOS technology with a reduced threshold voltage of 0.2 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.7 pp.925-933
- Publication Date
- 1996/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
- Category
- Logic
Authors
Keyword
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Yong MOON, Deog-kyoon JEONG, "An Efficient Charge Recovery Logic Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 7, pp. 925-933, July 1996, doi: .
Abstract: Efficient charge recovery logic(ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder(CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-µm CMOS technology with a reduced threshold voltage of 0.2 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_7_925/_p
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@ARTICLE{e79-c_7_925,
author={Yong MOON, Deog-kyoon JEONG, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Efficient Charge Recovery Logic Circuit},
year={1996},
volume={E79-C},
number={7},
pages={925-933},
abstract={Efficient charge recovery logic(ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder(CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-µm CMOS technology with a reduced threshold voltage of 0.2 V.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - An Efficient Charge Recovery Logic Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 925
EP - 933
AU - Yong MOON
AU - Deog-kyoon JEONG
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1996
AB - Efficient charge recovery logic(ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder(CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-µm CMOS technology with a reduced threshold voltage of 0.2 V.
ER -
English
