IEICE TRANSACTIONS on Electronics
Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC
Summary :
A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.6 pp.1172-1180
- Publication Date
- 2007/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.6.1172
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
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Yusuke IKEDA, Akira MATSUZAWA, "Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 6, pp. 1172-1180, June 2007, doi: 10.1093/ietele/e90-c.6.1172.
Abstract: A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.6.1172/_p
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@ARTICLE{e90-c_6_1172,
author={Yusuke IKEDA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC},
year={2007},
volume={E90-C},
number={6},
pages={1172-1180},
abstract={A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.},
keywords={},
doi={10.1093/ietele/e90-c.6.1172},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC
T2 - IEICE TRANSACTIONS on Electronics
SP - 1172
EP - 1180
AU - Yusuke IKEDA
AU - Akira MATSUZAWA
PY - 2007
DO - 10.1093/ietele/e90-c.6.1172
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2007
AB - A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.
ER -
English
