Over the past ten years, the demand for low-cost, low-power, and small form-factor portable wireless devices has led to the integration of RF transceivers on the same silicon as digital processors to form wireless systems-on-a-chip. This paper describes the challenges in designing CMOS systems-on-a-chip for wireless communications. RF transceiver building blocks for signal amplification, frequency translation, and frequency selectivity are examined with special emphasis on low noise amplifiers, power amplifiers, mixers, and frequency synthesizers. System-on-a-chip integration issues such as leakage currents of digital logic, calibration techniques, and noise coupling are also discussed.

Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.

An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-µm CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm² and 1.6 W, respectively.

In this paper, we discuss the effects of switch resistances on the step response of switched-capacitor (SC) circuits, especially multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters. Theory and simulation results reveal that the settling time of MDACs can be decreased by optimizing the switch resistances. This switch resistance optimization does not only effectively increase the speed of single-bit MDACs, but also of multi-bit MDACs. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. With such an optimization, the response of the switch will be improved by up to 50%.

A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.

We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the ΔΣ modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two nine-level quantizers and four DACs are used in the modulator for low-power implementations and higher signal-to-noise-and-distortion (SNDR), but the nonlinearities of DACs are not noise-shaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18 µm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm². These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to low-IF receivers in wireless communication systems.

A highly multi-channel on-chip signal monitor and off-chip waveform acquisition processor established analog circuit diagnosis against environmental disturbances in SoC. An array of 53 distributed probes followed by a single shared waveform acquisition kernel is embedded in a 0.18-µm CMOS experimental on-chip test bench. In combination with the off-chip processor materialized in FPGA and a host PC, fully automated on-chip waveform monitoring achieves high-throughput data acquisition of 300 ms per sample point with adaptive 10-bit timing and voltage resolutions at a minimum LSB of 100 ps and 400 µV, respectively. Analog signals of interest in a 1.5-bit conversion stage of a pipeline ADC were evaluated in terms of their response to substrate noises that globally existed in a chip. On-chip diagnosis derives in-depth findings relating to dynamic, large-signal, and sensitive behaviors of analog circuits in a real SoC environment, far beyond simulations with inevitably limited capacity.

It is an innovative idea for modern PLL generation to control the bandwidth proportionally to the reference frequency. Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. A new compact switched capacitor (SC) filter which has fully flat response has been developed for adaptive biased PLLs. We have also developed a new digital control method for achieving the wider frequency range. The measured performances of the test chip were good enough for the use in the microprocessors.

This paper describes a broadband active terminal circuit and its application to a distributed amplifier. In this study, we first analyzed and compared three types of active terminal circuits using representative circuit configurations, namely, an active terminal circuit with a common-emitter BJT, an active terminal circuit with a Darlington BJT pair, and an active terminal circuit with cascode-connected BJTs. The simulation results showed that the active terminal circuit with cascode-connected BJTs kept the matching condition up to high frequency. After the simulation, we fabricated a distributed amplifier that used an active terminal circuit with cascode-connected BJTs. The RF amplifier achieved a flat gain of 9.7 1.0 dB over a range of 3-15 GHz.

A new method of cancellation of IM3 using current feedback has been proposed for a multi-stage RFIC amplifier. In order to cancel the IM3 present in an output signal of the amplifier, the IIP3 level and IM3 phase of the amplifier are adjusted by means of feedback circuit techniques, so that the target specification is satisfied. By estimating the IIP3 level and IM3 phase variations for two states in situations with and without feedback possessing linear factors, the parameters of a feedback circuit can be calculated. To confirm the validity of the method, we have investigated two approaches; one including an analytical approach to designing a two-stage feedback amplifier, achieving an IIP3 level improvement of 14.8 dB. The other method involves the fabrication of single-stage amplifiers with and without feedback, operating at 850 MHz, both of which were designed as an integrated circuit using a 0.18 µm SiGe BiCMOS process. The fabricated IC's were tested using a load-pull measurement system, and a good agreement between the estimated and measured IIP3 level and IM3 phase variations has been achieved. Further studies show that the error in these variations, as estimated by the method, has been found to be less than 1.5 dB and 15 degrees, respectively, when the load admittance at 1701 MHz was greater than 1/50 S.

This paper describes miniaturized broadband lumped-element in-phase power dividers. We first propose two types of miniaturized broadband lumped-element in-phase power dividers composed of two inductors, a resistor, and two capacitors. Next, we use a simulation to compare these dividers with conventional power dividers. The simulation results reveal that the proposed lumped-element in-phase power dividers can help miniaturize circuits (by decreasing inductances by about 30%, reducing the number of necessary capacitors by half, and decreasing necessary capacitances by about 30% as compared to conventional lumped-element dividers) and attain broadband frequency characteristics (by increasing normalized operating frequency bandwidths (f/f₀) by about 80% as compared to conventional lumped-element dividers).

A 5-GHz-band highly linear frequency tuning voltage-controlled oscillator (VCO) using 0.35 µm SiGe BiCMOS technology is presented. The highly linear VCO has a novel resonant circuit that includes two spiral inductors, p-n junction diode varactor units and a voltage-level- shift circuit. The fabricated VCO exhibits a VCO gain from 224 to 341 MHz/V, giving a Kvco ratio of 1.5, which is less than one-half of that of a conventional VCO. The measured phase noise is -116 dBc/Hz at 1 MHz offset at an oscillation frequency of 5.5 GHz. The tuning range is from 5.45 to 5.95 GHz. The dc current consumption is 3.4 mA at a supply voltage of 3.0 V.

The linearity and noise required by GSM and UMTS receivers make the design of a CMOS mixer for these applications so challenging. A new technique for IP2 improvement in Zero-IF active mixers is presented in this paper. This inductor-less technique is based on canceling the parasitic capacitor of common source node of the switching transistors and synthesizing resistive impedance. Using this technique, a reconfigurable down converter mixer works from 900 MHz to 2.4 GHz is designed supporting GSM, DCS, PCS, UMTS and IEEE802.11 b-g standards. The mixer IIP2 is higher than 71 dBm in GSM and UMTS bands. The mixer conversion gain is higher that 12 dB in all frequency bands. The design is done in 65 nm CMOS technology and consumes 10 mA from a 1.2 V supply. The design meets the performance required for all mentioned standards, while its area and power is comparable with high performance single band mixers.

A quadrature demodulator (QDEMOD) for WCDMA direct-conversion receiver using a common-base input stage is reported. A common-base input stage is robust to parasitic elements and is suitable for integrating on-chip matching circuits to realize small and low-cost RF front-end modules. However, a common-mode blocker signal, such as the transmitter (TX) leakage signal, degrades the noise performance due to DC current increase and intermodulation distortion of the TX leakage signal and noise. We propose a QDEMOD with a common-base input stage capable of suppressing the TX leakage signal using symmetrical inductors. The QDEMOD was fabricated using SiGe BiCMOS process with f_T of 75 GHz. The measured results show that the NF degradation does not occur until the TX leakage signal input is larger than -10 dBm.

A fast f_c automatic tuning circuit suitable for WCDMA systems is proposed. The circuit employs master-slave architecture using digitally controlled G_m-C filter for avoiding long transient response. The tuning feedback loop contains a 2-bit up-down counter ADC for fast tuning operation. Furthermore, to avoid degradation of f_c tuning accuracy due to reference feedthrough, an analog loop filter with notch located near reference frequency is used. The fast f_c automatic tuning circuit is fabricated in a SiGe BiCMOS process. The tuning time within 200 µs is achieved for 35 chips from 2 lots and the standard deviation of 25.5 kHz is obtained for the average f_c of 2.12 MHz.

In this paper, a new operational amplifier is presented that improves the specifications such as dc gain, common mode rejection ratio. To obtain these improvements, we have used the two important concepts of feedback and bulk amplification.

This paper presents a new Fuzzy Logic Controller (FLC) having the ability to support rational-powered membership functions. These functions are extended forms of triangular/trapezoidal membership functions, and also those functions which are generated by applying linguistic hedges. A two-input, single-output, nine-rule Takagi-Sugeno-Kang (TSK) type FLC is designed in 0.35 µm standard CMOS technology. This controller can also be used as a standard (Mamdani) type FLC having singleton output membership functions, as well as a Linguistic Hedge FLC (LHFLC). Mixed analog/digital realization of the circuit makes the design programmable and extendable, while having relatively low power consumption. Current mode realization of the circuits leads to simple and intuitive configurations. For a particular set of programming parameters, simulation results of the controller using HSPICE simulator and level 49 parameters (BSIM3v3), show an average power consumption of 5 mW, and an RMS error of 1.32% compared to ideal results obtained from MATLAB software.

This paper discusses the resistive termination of on-chip high-performance interconnects. Resistive termination is effective to improve the bandwidth of on-chip interconnects, on the other hands, increases the power dissipation and the area. Therefore trade-off analysis about resistive termination is necessary. This paper proposes a method to determine the termination of on-chip interconnects. The termination derived by the proposed method provides minimum sensitivity to process variation as well as maximum eye-opening in voltage.

This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.

Power supply noise waveforms are acquired in a voltage domain by an on-chip monitor at resolutions of 0.3 ns/1.2 mV, in a digital test circuit consisting of 0.18-µm CMOS standard logic cells. Concurrently, magnetic field variation on a printed circuit board (PCB) due to power supply current of the test circuit is measured by an off-chip magnetic probing technique. An equivalent circuit model that unifies on- and off-chip impedance network of the entire test setup for EMI analysis is used for calculating the on-chip voltage-mode power supply noise from the off-chip magnetic field measurements. We have confirmed excellent consistency in frequency components of power supply noises up to 300 MHz among those derived by the on-chip direct sensing and the off-chip magnetic probing techniques. These results not only validate the state-of-the art EMI analysis methodology but also promise its connectivity with on-chip power supply integrity analysis at the integrated circuit level, for the first time in both technical fields.

This paper presents an automated design of linear and non-linear differential analog circuits accelerated by reuse of genetic operations. The system first synthesizes circuits using pairs of simplified MOSFET model. During the evolutionary process, genetic operations that improve circuit characteristics are stored in a database and reused to effectively obtain a better circuit. Simplified elements in a generated circuit are replaced by MOSFETs and optimization of the transistor size is performed using an optimizer available in market if necessary. The capability of this method is demonstrated through experiments of synthesis of a differential voltage amplifier, a circuit having cube-law characteristic in differential mode and square-law characteristic in common-mode, and a dB-linear VGA (Variable Gain Amplifier). The results show the reuse of genetic operations accelerates the synthesis and success rate becomes 100%.

An integrated multi-level simulation environment is developed for a highly collision-resistant RFID system. An analog/mixed-signal (AMS) simulator for a circuit-level description of analog front-end power/signal transmission through electro-magnetic coupling is concurrently connected to a tailored software simulator for system-level description of digital back-end processing of TH-CDMA based anti-collision communication. The feasibility of the RFID system in which more than 1,000 transponders can be identified by a single reader in 400 msec is successfuly explored, under a practical presence of field disturbances such as background noises in communication channels as well as variations of electro-magnetic coupling strengths for power transmission.

A 1-V operational sigma-delta modulator with a second-order passive switched capacitor filter is designed and fabricated by using a 90 nm CMOS process. No gate-voltage bootstrapped scheme is adopted to drive analog switches, and the voltage gain of a comparator is chosen to be 94 dB. The experimental results show that the peak SNR reached 68.9 dB with a frequency bandwidth of 40 kHz when the clock was 40 MHz.

For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.

Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.

This paper presents a novel method to increase an impedance of a current source. The proposed circuit with a cascode and gain-boosting configuration is also presented. The operation has been confirmed by simulation using a 0.18 µm CMOS technology.

Long-period gratings (LPGs) are written in the fibers un-preheated and preheated. The influence of residual stress on trimming resonance wavelengths by heating the LPGs is investigated comparing the post-heating changes of the transmission characteristics. It becomes evident that the residual stress relaxation shifts resonance wavelengths to shorter wavelengths quickly and the glass structure modification moves them to longer wavelengths slowly. The relaxation rate of the glass structure drops rapidly with the decrease in heating temperature, and the influence of the residual stress relaxation appears more strongly at the early stage of heating at a lower temperature. The trimming wavelength range can be broadened on the short wavelength side by decreasing the heating temperature. We could adjust resonance wavelengths without significant peak loss changes by the residual stress relaxation before writing LPGs, though the trimming range becomes narrow.

We have numerically evaluated the filtering characteristics of two vertically coupled microring resonator filters. In this evaluation we used the finite-difference time-domain method as the numerical analysis method. The structure we designed allows only a specific wavelength to pass. The filtering characteristics of this structure can be altered by changing the layout of the microring resonator. By using this structure the interval between peak wavelengths at a specific wavelength in the output spectrum can be increased. Specifically, the interval between peak wavelengths can be increased from 20 nm to 40 nm at wavelengths near 1.46 µm.

In this paper, we report on the transmission characteristics of transformers of a RF splitter widely used in CATV systems. From the point of view of broadening the splitter's operating frequency, the relationship between the RF transformer's transmission characteristics and design parameters has been investigated using computer-aided engineering. Based on the calculations, a sample device has been fabricated to confirm the theoretical results. It has been found that the configulation of the transformer winding is the most important factor affecting device performance. By selecting the appropriate winding, excessive loss can be suppressed to less than 1.6 dB and 3 dB in a frequency range of 20 MHz to 2,600 MHz for the cases of 2-way and 4-way splitters, respectively.

A circuit design of a CMOS integrable heartbeat spike-pulse detection circuit is proposed in this paper. This circuit is developed to be implemented on a small-sized RFID sensor tag (which we call a smart RFID tag throughout this paper) implanted in a transgenic mouse. This circuit can detect only spike pulses with magnitude higher than the prescribed level from a mouse's heartbeat signal, which is sensed by a small microphone sensor and/or an electrocardiogram (ECG) microsensor attached to the RFID tag. The proposed circuit features robustness to the device tolerances and temperature variations thanks to its auto-bias technique based on good device matching and its switched-capacitor auto offset-canceling technique. The circuit was fabricated by a standard 0.35 µm CMOS process and works at a supply voltage of 3 V and dissipates less than 800 µW.