IEICE TRANSACTIONS on Electronics
Evaluation of Digitally Controlled PLL by Clock-Period Comparison
Summary :
For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.6 pp.1307-1310
- Publication Date
- 2007/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.6.1307
- Type of Manuscript
- Special Section LETTER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Keyword
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Yukinobu MAKIHARA, Masayuki IKEBE, Eiichi SANO, "Evaluation of Digitally Controlled PLL by Clock-Period Comparison" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 6, pp. 1307-1310, June 2007, doi: 10.1093/ietele/e90-c.6.1307.
Abstract: For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.6.1307/_p
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@ARTICLE{e90-c_6_1307,
author={Yukinobu MAKIHARA, Masayuki IKEBE, Eiichi SANO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Evaluation of Digitally Controlled PLL by Clock-Period Comparison},
year={2007},
volume={E90-C},
number={6},
pages={1307-1310},
abstract={For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.},
keywords={},
doi={10.1093/ietele/e90-c.6.1307},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Evaluation of Digitally Controlled PLL by Clock-Period Comparison
T2 - IEICE TRANSACTIONS on Electronics
SP - 1307
EP - 1310
AU - Yukinobu MAKIHARA
AU - Masayuki IKEBE
AU - Eiichi SANO
PY - 2007
DO - 10.1093/ietele/e90-c.6.1307
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2007
AB - For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.
ER -
English
