Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver
Summary :
This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.6 pp.1274-1281
- Publication Date
- 2007/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.6.1274
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Takeshi KUBOKI, Akira TSUCHIYA, Hidetoshi ONODERA, "Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 6, pp. 1274-1281, June 2007, doi: 10.1093/ietele/e90-c.6.1274.
Abstract: This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.6.1274/_p
Copy
@ARTICLE{e90-c_6_1274,
author={Takeshi KUBOKI, Akira TSUCHIYA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver},
year={2007},
volume={E90-C},
number={6},
pages={1274-1281},
abstract={This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.},
keywords={},
doi={10.1093/ietele/e90-c.6.1274},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver
T2 - IEICE TRANSACTIONS on Electronics
SP - 1274
EP - 1281
AU - Takeshi KUBOKI
AU - Akira TSUCHIYA
AU - Hidetoshi ONODERA
PY - 2007
DO - 10.1093/ietele/e90-c.6.1274
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2007
AB - This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip transmission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.
ER -
English
