Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

Atsushi IWATA; Takeshi YOSHIDA; Mamoru SASAKI

doi:10.1093/ietele/e90-c.6.1149

Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

Atsushi IWATA, Takeshi YOSHIDA, Mamoru SASAKI

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Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.6 pp.1149-1155

Publication Date: 2007/06/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.6.1149

Type of Manuscript: Special Section INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Atsushi IWATA, Takeshi YOSHIDA, Mamoru SASAKI, "Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 6, pp. 1149-1155, June 2007, doi: 10.1093/ietele/e90-c.6.1149.
Abstract: Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.6.1149/_p

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@ARTICLE{e90-c_6_1149,
author={Atsushi IWATA, Takeshi YOSHIDA, Mamoru SASAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices},
year={2007},
volume={E90-C},
number={6},
pages={1149-1155},
abstract={Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.},
keywords={},
doi={10.1093/ietele/e90-c.6.1149},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 1149
EP - 1155
AU - Atsushi IWATA
AU - Takeshi YOSHIDA
AU - Mamoru SASAKI
PY - 2007
DO - 10.1093/ietele/e90-c.6.1149
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2007
AB - Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.
ER -