This paper presents a multi-channel biomedical sensor system with system-level chopping and stochastic analog-to-digital (A/D) conversion techniques. The system-level chopping technique extends the input-signal bandwidth and reduces the interchannel crosstalk caused by multiplexing. The system-level chopping can replace an analog low-pass filter (LPF) with a digital filter and can reduce its area occupation. The stochastic A/D conversion technique realizes power-efficient resolution enhancement. A novel auto-calibration technique is also proposed for the stochastic A/D conversion technique. The proposed system includes a prototype analog front-end (AFE) IC fabricated using a 130 nm CMOS process. The fabricated AFE IC improved its interchannel crosstalk by 40 dB compared with the conventional analog chopping architecture. The AFE IC achieved SNDR of 62.9 dB at a sampling rate of 31.25 kSps while consuming 9.6 μW from a 1.2 V power supply. The proposed resolution enhancement technique improved the measured SNDR by 4.5 dB.

Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.