This paper demonstrates 300GHz terahertz wireless communication using CMOS transmitter (TX) and receiver (RX) modules targeting sixth-generation (6G). To extend communication distance, CMOS modules with WR-3.4 waveguide interface and a high-gain antenna of 40dBi Cassegrain antenna are designed, achieving 36Gbps throughput at a 1m communication distance. Besides, in order to support orthogonal frequency-division multiplexing (OFDM), a self-heterodyne architecture is introduced, which effectively cancels the phase noise in multi-carrier modulation. As a proof-of-concept (PoC), the paper successfully demonstrates real-time video transfer at a 10m communication distance using fifth-generation (5G) based OFDM at the 300GHz frequency band.

There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modeling techniques. Low-power high-speed wireless data transfer at 11Gb/s and 19pJ/bit and a 7-pJ/bit ultra-low-power transceiver chipset are presented.

This paper presents low-noise amplifier (LNA)-less 300-GHz CMOS receivers that operate above the NMOS unity-power-gain frequency, fmax. The receivers consist of a down-conversion mixer with a doubler- or tripler-last multiplier chain that upconverts an LO1/n signal into 300 GHz. The conversion gain of the receiver with the doubler-last multiplier is -19.5 dB and its noise figure, 3-dB bandwidth, and power consumption are 27 dB, 27 GHz, and 0.65 W, respectively. The conversion gain of the receiver with the tripler-last multiplier is -18 dB and its noise figure, 3-dB bandwidth, and power consumption are 25.5 dB, 33 GHz, and 0.41 W, respectively. The receivers achieve a wireless data rate of 32 Gb/s with 16QAM. This shows the potential of the moderate-fmax CMOS technology for ultrahigh-speed THz wireless communications.

A 250-MIPS, 125-MFLOPS peak performance processing element (PE), which is being developed for an on-chip multiprocessor, has been modeled and evaluated. The PE includes the following new architecture components: an FPU shared by several IUs in order to increase the efficiency of the FPU pipelines, an on-chip data cache with a prefetch mechanism to reduce clock cycles waiting for memory, and an interface to high speed DRAM, such as Rambus DRAM and Synchronous DRAM. As a result, a PE model with an FPU shared by four or eight IUs causes only 10% performance reduction compared to a model with an un-shared FPU model while saving the cost of three FPUs. Furthermore, a PE model with prefetch operates 1.2 to 1.8 times faster than a model without prefetch at 250-MHz clock rate when the Rambus DRAM is connected. It becomes clear that this PE architecture can bring a high effective performance at over 250-MHz, and is cost-effective for the on-chip multiprocessor.

This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

A neural-signal sensing system with multi-input-channels was designed utilizing a new chopper amplifier with direct connected to a multiplexer. The proposed system consists of multiplexers, chopper amplifiers, a multi-mode analog-to-digital converter (ADC), and a wireless transmitter. It enables to measure 50-channel signals at the same time, which are selected out of 100 channels to detect useful information. The test chip including 10-channel-inputs chopper-amplifier and multi-mode ADC, that was designed and fabricated with a mixed signal 0.35-µm CMOS technology. Utilizing the proposed direct chopper input scheme and the shared chopper amplifier, the circuits was designed with a small area of 9.4 mm2. High accuracy channel selecting and multiplexing operations were confirmed, and an equivalent input noise of 10-nV/root-Hz was obtained with test chip measurements. Power dissipation of the chopper amplifier and the ADC were 6.0-mW and 2.5-mW at a 3-V supply voltage, respectively.

L-type LC/CL matching circuits are well known for their simple analytical solutions and have been applied to many radio-frequency (RF) circuits. When actually constructing a circuit, parasitic elements are added to inductors and capacitors. Therefore, each L and C element has a self-resonant frequency, which affects the characteristics of the matching circuit. In this paper, the parallel parasitic capacitance to the inductor and the series parasitic inductor to the capacitance are taken up as parasitic elements, and the details of the effects of the self-resonant frequency of each element on the S11, voltage standing wave ratio (VSWR) and S21 characteristics are reported. When a parasitic element is added, each characteristic basically tends to deteriorate as the self-resonant frequency decreases. However, as an interesting feature, we found that the combination of resonant frequencies determines the VSWR and passband characteristics, regardless of whether it is the inductor or the capacitor.

We propose a neural-sensing LSI with a bi-directional wireless interface, which is capable of detecting 5-channel neural signals in a living animal. The proposed sensing LSI consists of a multiplexer with 5-channels selectable from 10 channels, a chopper amplifier using a new direct-chopper-input scheme, a programmable multi-mode analog-to-digital converter (ADC), and a wireless-transmitter/receiver with BPSK modulation signals. The test-chip was implemented by mixed-signal 0.35-µm CMOS technology. We measured the test chip and confirmed basic operations of these blocks. The chopper-amplifier achieved 66-dB DC gain, bandwidth of 400 kHz, and 4-µV noise with power dissipation of 6-mW with a 3-V supply. We observed real nerve signals in a living cricket using the proposed chopper amplifier. ADC achieved 52-ksps operation with power dissipation of 0.43-mW at 3-V supply. The wireless transmitter achieved 1-Mbps data transmission at a distance of 1-m with 1.5-mW power dissipation at 3-V supply.

To detect neural spike signals, low-power neural signal recording frontend circuits must amplify neural signals with below 100 µV amplitude and a few hundred Hz frequency while suppressing a large DC offset voltage, 1/f noise of MOSFETs, and induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18-µm CMOS technology. The voltage gain of 39 dB at the bandwidth of the neural signal and the gain reduction of 20 dB at AC supply noise of 60 Hz were obtained. The input equivalent noise and power dissipation were 90 nV/root-Hz and 90 µW at a supply voltage of 1.5 V, respectively.

A power-scalable wideband distributed amplifier is proposed. For reducing the power consumption of this power-hungry amplifier, it is efficient to lower the supply voltage. However, there is a hurdle owing to the transistor threshold voltage. In this work, a CMOS deeply depleted channel process is employed to overcome the hurdle.

Recently low-voltage and low-noise analog circuits with sub 100-nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1 V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18-µm CMOS was measured at a 0.6-V supply, and achieved 89-nV/ input referred noise (at 100 Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/f-noise reduction techniques are described. The ring VCO test chip achieves 1-GHz oscillation, -68 dBc/Hz at 100-kHz offset, 710-µW power dissipation at 1-V power supply.

Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-µm CMOS technology achieved 50-nV/Hz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.

The brain-machine interface (BMI) is a new method for man-machine interface, which enables us to control machines and to communicate with others, without input devices but directly using brain signals. Previously, we successfully developed a real time control system for operating a robot arm using brain-machine interfaces based on the brain surface electrodes, with the purpose of restoring motor and communication functions in severely disabled people such as amyotrophic lateral sclerosis patients. A fully-implantable wireless system is indispensable for the clinical application of invasive BMI in order to reduce the risk of infection. This system includes many new technologies such as two 64-channel integrated analog amplifier chips, a Bluetooth wireless data transfer circuit, a wirelessly rechargeable battery, 3 dimensional tissue-fitting high density electrodes, a titanium head casing, and a fluorine polymer body casing. This paper describes key features of the first prototype of the BMI system for clinical application.

This paper presents a wideband differential amplifier operating at 141GHz in 40-nm CMOS. It is composed of five differential common source stages with cross-coupled capacitors. A small-signal gain of 20dB and a 3-dB bandwidth of 22GHz are achieved. It consumes 75mW from a 0.94-V voltage supply. The die area with balun and pads is 945×842µm2 and the size of the core not including input/output matching networks is 201×284µm2. The small core area is made possible by using a refined “fishbone” layout technique.