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Takeshi YOSHIDA Yoshihiro MASUI Ryoji EKI Atsushi IWATA Masayuki YOSHIDA Kazumasa UEMATSU
To detect neural spike signals, low-power neural signal recording frontend circuits must amplify neural signals with below 100 µV amplitude and a few hundred Hz frequency while suppressing a large DC offset voltage, 1/f noise of MOSFETs, and induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18-µm CMOS technology. The voltage gain of 39 dB at the bandwidth of the neural signal and the gain reduction of 20 dB at AC supply noise of 60 Hz were obtained. The input equivalent noise and power dissipation were 90 nV/root-Hz and 90 µW at a supply voltage of 1.5 V, respectively.