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Yohei MORISHITA Sangyeop LEE Toshihiro TERAOKA Ruibing DONG Yuichi KASHINO Hitoshi ASANO Shinsuke HARA Kyoya TAKANO Kosuke KATAYAMA Takenori SAKAMOTO Naganori SHIRAKATA Koji TAKINAMI Kazuaki TAKAHASHI Akifumi KASAMATSU Takeshi YOSHIDA Shuhei AMAKAWA Minoru FUJISHIMA
This paper demonstrates 300GHz terahertz wireless communication using CMOS transmitter (TX) and receiver (RX) modules targeting sixth-generation (6G). To extend communication distance, CMOS modules with WR-3.4 waveguide interface and a high-gain antenna of 40dBi Cassegrain antenna are designed, achieving 36Gbps throughput at a 1m communication distance. Besides, in order to support orthogonal frequency-division multiplexing (OFDM), a self-heterodyne architecture is introduced, which effectively cancels the phase noise in multi-carrier modulation. As a proof-of-concept (PoC), the paper successfully demonstrates real-time video transfer at a 10m communication distance using fifth-generation (5G) based OFDM at the 300GHz frequency band.
Shinsuke HARA Kosuke KATAYAMA Kyoya TAKANO Ruibing DONG Issei WATANABE Norihiko SEKINE Akifumi KASAMATSU Takeshi YOSHIDA Shuhei AMAKAWA Minoru FUJISHIMA
This paper presents low-noise amplifier (LNA)-less 300-GHz CMOS receivers that operate above the NMOS unity-power-gain frequency, fmax. The receivers consist of a down-conversion mixer with a doubler- or tripler-last multiplier chain that upconverts an LO1/n signal into 300 GHz. The conversion gain of the receiver with the doubler-last multiplier is -19.5 dB and its noise figure, 3-dB bandwidth, and power consumption are 27 dB, 27 GHz, and 0.65 W, respectively. The conversion gain of the receiver with the tripler-last multiplier is -18 dB and its noise figure, 3-dB bandwidth, and power consumption are 25.5 dB, 33 GHz, and 0.41 W, respectively. The receivers achieve a wireless data rate of 32 Gb/s with 16QAM. This shows the potential of the moderate-fmax CMOS technology for ultrahigh-speed THz wireless communications.
Ramesh K. POKHAREL Xin LIU Dayang A.A. MAT Ruibing DONG Haruichi KANAYA Keiji YOSHIDA
This paper presents the design of a second-order and a fourth-order bandpass filter (BPF) for 60 GHz millimeter-wave applications in 0.18 µm CMOS technology. The proposed on-chip BPFs employ the folded open loop structure designed on pattern ground shields. The adoption of a folded structure and utilization of multiple transmission zeros in the stopband permit the compact size and high selectivity for the BPF. Moreover, the pattern ground shields obviously slow down the guided waves which enable further reduction in the physical length of the resonator, and this, in turn, results in improvement of the insertion losses. A very good agreement between the electromagnetic (EM) simulations and measurement results has been achieved. As a result, the second-order BPF has the center frequency of 57.5 GHz, insertion loss of 2.77 dB, bandwidth of 14 GHz, return loss less than 27.5 dB and chip size of 650 µm810 µm (including bonding pads) while the fourth-order BPF has the center frequency of 57 GHz, insertion loss of 3.06 dB, bandwidth of 12 GHz, return loss less than 30 dB with chip size of 905 µm810 µm (including bonding pads).