This paper demonstrates 300GHz terahertz wireless communication using CMOS transmitter (TX) and receiver (RX) modules targeting sixth-generation (6G). To extend communication distance, CMOS modules with WR-3.4 waveguide interface and a high-gain antenna of 40dBi Cassegrain antenna are designed, achieving 36Gbps throughput at a 1m communication distance. Besides, in order to support orthogonal frequency-division multiplexing (OFDM), a self-heterodyne architecture is introduced, which effectively cancels the phase noise in multi-carrier modulation. As a proof-of-concept (PoC), the paper successfully demonstrates real-time video transfer at a 10m communication distance using fifth-generation (5G) based OFDM at the 300GHz frequency band.

On-chip transmission lines are widely used in ultrahigh-frequency integrated circuits. One of the issues in modeling such transmission lines is that no reference impedance can be established on a chip. Conventionally, the parallel admittance Yp has been adopted as a reference parameter for on-chip transmission lines instead of a reference characteristic impedance of 50Ω. In the case of CMOS processes, however, Yp can have complicated characteristics in the short-millimeter-wave band owing to the frequency characteristics of the electric permittivity of low-k materials, which cannot be expressed using a simple circuit. To solve this problem, we propose the use of the series impedance Zs as a reference parameter for transmission-line modeling since it basically can be determined from the geometrical dimensions and the frequency-stable permeability and resistivity. The parameters of transmission lines obtained by the proposed method were compared with those obtained by conventional methods using a 40nm CMOS process. By using the equivalent circuit model of Yp along with RLC resonators, it is shown that the peaks of the frequency characteristics of Yp can be used to explain the absorption spectrum of the dielectric. This suggests that the proposed method is suitable for CMOS short-millimeter-wave transmission lines.

The performances of an SET required for integration are discussed. Conventional SETs had several problems such as large leakage current, insufficient voltage gain and so on. To overcome these problems, a new SET utilizing Schottky barriers as tunnel junctions is proposed. Its current characteristics and Coulomb-blockade conditions are calculated and the effectiveness for an integrated device is discussed.

Frequencies around 300GHz offer extremely broad atmospheric transmission window with relatively low losses of up to 10dB/km and can be regarded as the ultimate platform for ultrahigh-speed wireless communications with near-fiber-optic data rates. This paper reviews technical challenges and recent advances in integrated circuits targeted at communications using these and nearby “terahertz (THz)” frequencies. Possible new applications of THz wireless links that are hard to realize by other means are also discussed.

There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modeling techniques. Low-power high-speed wireless data transfer at 11Gb/s and 19pJ/bit and a 7-pJ/bit ultra-low-power transceiver chipset are presented.

As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SDR), cognitive radios (CR), and reconfigurable radios (RR); (ii) systems that operate in the millimeter-wave or terahertz-wave region and achieve high speed and large-capacity data transmission; and (iii) microminiaturized low-power RF communication systems that will be extensively used in our everyday lives. However, classical technology for designing analog RF circuits cannot be used to design circuits for the abovementioned devices since it can be applied only in the case of continuous voltage and continuous time signals; therefore, it is necessary to integrate the design of high-speed digital circuits, which is based on the use of discrete voltages and the discrete time domain, with analog design, in order to both achieve wideband operation and compensate for signal distortions as well as variations in process, power supply voltage, and temperature. Moreover, as it is thought that small integration of the antenna and the interface circuit is indispensable to achieve miniaturized micro RF communication systems, the construction of the integrated design environment with the Micro Electro Mechanical Systems (MEMS) device etc. of the different kind devices becomes more important. In this paper, the history and the current status of the development of RF CMOS circuits are reviewed, and the future status of RF CMOS circuits is predicted.

This paper presents low-noise amplifier (LNA)-less 300-GHz CMOS receivers that operate above the NMOS unity-power-gain frequency, fmax. The receivers consist of a down-conversion mixer with a doubler- or tripler-last multiplier chain that upconverts an LO1/n signal into 300 GHz. The conversion gain of the receiver with the doubler-last multiplier is -19.5 dB and its noise figure, 3-dB bandwidth, and power consumption are 27 dB, 27 GHz, and 0.65 W, respectively. The conversion gain of the receiver with the tripler-last multiplier is -18 dB and its noise figure, 3-dB bandwidth, and power consumption are 25.5 dB, 33 GHz, and 0.41 W, respectively. The receivers achieve a wireless data rate of 32 Gb/s with 16QAM. This shows the potential of the moderate-fmax CMOS technology for ultrahigh-speed THz wireless communications.

This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).

E-band communication is allocated to the frequency bands of 71-76 and 81-86GHz. Radio-frequency (RF) front-end components for E-band communication have been realized using compound semiconductor technology. To realize a CMOS LNA for E-band communication, we propose a gain-boosted cascode amplifier (GBCA) stage that simultaneously provides high gain and stability. Designing an LNA from scratch requires considerable time because the tuning of matching networks with consideration of the parasitic elements is complicated. In this paper, we model the characteristics of devices including the effects of their parasitic elements. Using these models, an optimizer can estimate the characteristic of a designed LNA precisely without electromagnetic simulations and gives us the design values of an LNA when the layout constraint is ignored. Starting from the values, a four-stage LNA with a GBCA stage is designed very easily even though the layout constraint is considered and fabricated by a 65nm LP CMOS process. The fabricated LNA is measured, and it is confirmed that it achieves 18.5GHz bandwidth and over 24.3dB gain with 50.6mW power consumption. This is the first LNA to achieve a gain bandwidth of over 300GHz in the E-band among the LNAs utilizing any kind of semiconductor technologies. In this paper, we have proved that CMOS technology, which is suitable for baseband and digital circuitry, is applicable to a communication system covering the entire E-band.

The most commonly used scattering parameters (S parameters) are normalized to a real reference resistance, typically 50Ω. In some cases, the use of S parameters normalized to some complex reference impedance is essential or convenient. But there are different definitions of complex-referenced S parameters that are incompatible with each other and serve different purposes. To make matters worse, different simulators implement different ones and which ones are implemented is rarely properly documented. What are possible scenarios in which using the right one matters? This tutorial-style paper is meant as an informal and not overly technical exposition of some such confusing aspects of S parameters, for those who have a basic familiarity with the ordinary, real-referenced S parameters.

A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, <110> and <100>, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to 20% and 50 mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

A power-scalable wideband distributed amplifier is proposed. For reducing the power consumption of this power-hungry amplifier, it is efficient to lower the supply voltage. However, there is a hurdle owing to the transistor threshold voltage. In this work, a CMOS deeply depleted channel process is employed to overcome the hurdle.

Various techniques of single-electron circuit simulation are presented. The subjects include visualization of state probabilities, accurate yet reasonably fast steady-state analysis and SPICE-based high-speed simulation for circuits composed of Single-Electron Transistors (SETs). The visualized state probabilities allow one to grasp the dynamics of a single-electron circuit intuitively. The new algorithm for steady-state analysis uses the master equation and Monte Carlo method in combination. We suppose this is the best way to perform steady-state analysis. The SPICE-based simulator significantly outperforms the conventional reference simulator in speed. It is, to the best of our knowledge, the only simulator that can simulate SET circuits for real applications. It also facilitates the study of the integration of SETs and MOSFETs.

A physics-based equivalent circuit model of the ceramic capacitor is proposed, which can reproduce frequency characteristics of its impedance including the often observed yet hitherto physically unexplained kinks appearing above the primary series resonance frequency. The model can also account for parasitic effects of external inductances. In order to efficiently analyze and gain engineering insight into ceramic capacitors with a large number of metallic laminae, a two-dimensional method of moments is developed that treats the laminar structure as a uniform, effective medium. It turns out that the primary resonance and the kinks can be well understood and modeled by a lossy transmission line stub with a drastic wavelength reduction. The capacitor model is completed by adding components describing the skin effect and external inductances. The modeled impedance stays within a 4% margin of error up to 5 GHz. The proposed model could greatly improve the accuracy of power distribution network simulation.

This paper presents a wideband differential amplifier operating at 141GHz in 40-nm CMOS. It is composed of five differential common source stages with cross-coupled capacitors. A small-signal gain of 20dB and a 3-dB bandwidth of 22GHz are achieved. It consumes 75mW from a 0.94-V voltage supply. The die area with balun and pads is 945×842µm2 and the size of the core not including input/output matching networks is 201×284µm2. The small core area is made possible by using a refined “fishbone” layout technique.