IEICE TRANSACTIONS on Electronics
A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC
Summary :
A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E106-C No.10 pp.533-537
- Publication Date
- 2023/10/01
- Publicized
- 2023/04/06
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2022CTS0001
- Type of Manuscript
- BRIEF PAPER
- Category
Authors
Sangyeop LEE
Hiroshima University
Kyoya TAKANO
Hiroshima University
Shuhei AMAKAWA
Hiroshima University
Takeshi YOSHIDA
Hiroshima University
Minoru FUJISHIMA
Hiroshima University
Keyword
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Sangyeop LEE, Kyoya TAKANO, Shuhei AMAKAWA, Takeshi YOSHIDA, Minoru FUJISHIMA, "A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 533-537, October 2023, doi: 10.1587/transele.2022CTS0001.
Abstract: A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTS0001/_p
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@ARTICLE{e106-c_10_533,
author={Sangyeop LEE, Kyoya TAKANO, Shuhei AMAKAWA, Takeshi YOSHIDA, Minoru FUJISHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC},
year={2023},
volume={E106-C},
number={10},
pages={533-537},
abstract={A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).},
keywords={},
doi={10.1587/transele.2022CTS0001},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC
T2 - IEICE TRANSACTIONS on Electronics
SP - 533
EP - 537
AU - Sangyeop LEE
AU - Kyoya TAKANO
AU - Shuhei AMAKAWA
AU - Takeshi YOSHIDA
AU - Minoru FUJISHIMA
PY - 2023
DO - 10.1587/transele.2022CTS0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).
ER -
English
