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Sangyeop LEE Shuhei AMAKAWA Takeshi YOSHIDA Minoru FUJISHIMA
A power-scalable wideband distributed amplifier is proposed. For reducing the power consumption of this power-hungry amplifier, it is efficient to lower the supply voltage. However, there is a hurdle owing to the transistor threshold voltage. In this work, a CMOS deeply depleted channel process is employed to overcome the hurdle.
Yohei MORISHITA Sangyeop LEE Toshihiro TERAOKA Ruibing DONG Yuichi KASHINO Hitoshi ASANO Shinsuke HARA Kyoya TAKANO Kosuke KATAYAMA Takenori SAKAMOTO Naganori SHIRAKATA Koji TAKINAMI Kazuaki TAKAHASHI Akifumi KASAMATSU Takeshi YOSHIDA Shuhei AMAKAWA Minoru FUJISHIMA
This paper demonstrates 300GHz terahertz wireless communication using CMOS transmitter (TX) and receiver (RX) modules targeting sixth-generation (6G). To extend communication distance, CMOS modules with WR-3.4 waveguide interface and a high-gain antenna of 40dBi Cassegrain antenna are designed, achieving 36Gbps throughput at a 1m communication distance. Besides, in order to support orthogonal frequency-division multiplexing (OFDM), a self-heterodyne architecture is introduced, which effectively cancels the phase noise in multi-carrier modulation. As a proof-of-concept (PoC), the paper successfully demonstrates real-time video transfer at a 10m communication distance using fifth-generation (5G) based OFDM at the 300GHz frequency band.
Sangyeop LEE Norifumi KANEMARU Sho IKEDA Tatsuya KAMIMURA Satoru TANOI Hiroyuki ITO Noboru ISHIHARA Kazuya MASU
This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.
Sho IKEDA Sangyeop LEE Tatsuya KAMIMURA Hiroyuki ITO Noboru ISHIHARA Kazuya MASU
This paper proposes an ultra-low-power 5.5-GHz PLL which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO with linearity-compensated varactor for low supply voltage operation. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The FBB is also employed for linear-frequency-tuning of VCO under low supply voltage of 0.5V. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The digital calibration circuit is introduced to control the lock-range of ILFD automatically. The proposed PLL was fabricated in a 65nm CMOS process. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106dBc/Hz at 5.5GHz output. The supply voltage is 0.54V for divider and 0.5V for other components. Total power consumption is 0.95mW.
Sangyeop LEE Shuhei AMAKAWA Takeshi YOSHIDA Minoru FUJISHIMA
This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.
Sangyeop LEE Kyoya TAKANO Shuhei AMAKAWA Takeshi YOSHIDA Minoru FUJISHIMA
A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).
Zixuan LI Sangyeop LEE Noboru ISHIHARA Hiroyuki ITO
A wireless sensor terminal module of 5cc size (2.5 cm × 2.5 cm × 0.8 cm) that does not require a battery is proposed by integrating three kinds of circuit technologies. (i) a low-power sensor interface: an FM modulation type CMOS sensor interface circuit that can operate with a typical power consumption of 24.5 μW was fabricated by the 0.7-μm CMOS process technology. (ii) power supply to the sensor interface circuit: a wireless power transmission characteristic to a small-sized PCB spiral coil antenna was clarified and applied to the module. (iii) wireless sensing from the module: backscatter communication technology that modulates the signal from the base terminal equipment with sensor information and reflects it, which is used for the low-power sensing operation. The module fabricated includes a rectifier circuit with the PCB spiral coil antenna that receives wireless power transmitted from base terminal equipment by electromagnetic resonance coupling and converts it into DC power and a sensor interface circuit that operates using the power. The interface circuit modulates the received signal with the sensor information and reflects it back to the base terminal. The module could achieve 100 mm communication distance when 0.4 mW power is feeding to the sensor terminal.