IEICE TRANSACTIONS on Electronics
A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS
Summary :
This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.10 pp.1589-1597
- Publication Date
- 2012/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.1589
- Type of Manuscript
- Special Section PAPER (Special Section on Recent Progress in Microwave and Millimeter-Wave Technologies)
- Category
Authors
Sangyeop LEE
Norifumi KANEMARU
Sho IKEDA
Tatsuya KAMIMURA
Satoru TANOI
Hiroyuki ITO
Noboru ISHIHARA
Kazuya MASU
Keyword
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Sangyeop LEE, Norifumi KANEMARU, Sho IKEDA, Tatsuya KAMIMURA, Satoru TANOI, Hiroyuki ITO, Noboru ISHIHARA, Kazuya MASU, "A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 10, pp. 1589-1597, October 2012, doi: 10.1587/transele.E95.C.1589.
Abstract: This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1589/_p
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@ARTICLE{e95-c_10_1589,
author={Sangyeop LEE, Norifumi KANEMARU, Sho IKEDA, Tatsuya KAMIMURA, Satoru TANOI, Hiroyuki ITO, Noboru ISHIHARA, Kazuya MASU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS},
year={2012},
volume={E95-C},
number={10},
pages={1589-1597},
abstract={This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.},
keywords={},
doi={10.1587/transele.E95.C.1589},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 1589
EP - 1597
AU - Sangyeop LEE
AU - Norifumi KANEMARU
AU - Sho IKEDA
AU - Tatsuya KAMIMURA
AU - Satoru TANOI
AU - Hiroyuki ITO
AU - Noboru ISHIHARA
AU - Kazuya MASU
PY - 2012
DO - 10.1587/transele.E95.C.1589
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2012
AB - This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -119 dBc/Hz.
ER -
English
