A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, <110> and <100>, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to 20% and 50 mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

A systematic experimental and modeling study is reported, which characterizes the low-frequency noise spectrum of 100 nm-MOSFETs accurately. Two kinds of measured spectra are observed: 1/f and non-1/f spectra. The non-1/f spectrum is analysed by forward and backward measurements with exchanged source and drain, and shown to be due to a randomly distributed inhomogeneity of the trap density along the channel and within the gate oxide. By averaging the spectra of identical MOSFETs on a wafer the measured non-1/f noise spectra reduce to a 1/f characteristics. On the basis of these measurement data a noise model for circuit simulation is developed, which reproduces the low-frequency noise spectrum with a single model parameter for all gate lengths and under any bias conditions.

Small-size MOSFETs are becoming core devices in RF applications because of improved high frequency characteristics. For reliable design of RF integrated circuits operating at the GHz range, accurate modeling of small-size MOSFET characteristics is indispensable. In MOSFETs with reduced gate length (Lg), the lateral field along the MOSFET channel is becoming more pronounced, causing short-channel effects. These effects should be included in the device modeling used for circuit simulation. In this work, we investigated the effects of the field gradient in the gate-drain capacitance (Cgd). 2-Dimensional (2D) simulations done with MEDICI show that the field gradient, as it influences the channel condition, induces a capacitance which is visible in the MOSFET saturation operation. Changes in Cgd is incorporated in the modeling by an induced capacitance approach. The new approach has been successfully implemented in the surface-potential based model HiSIM (Hiroshima-university STARC IGFET Model) and is capable of reproducing accurately the measured Cgd-Lg characteristics, which are particularly significant for pocket-implant technology. Results show that pocket-implantation introduces a steep potential increase near the drain region, which results to a shift of the Cgd transition region (from linear to saturation) to lower bias voltages. Cgd at saturation decreases with Lg due to steeper surface potential and increased impurity concentration effects at reduced Lg.

We have developed a model for circuit-simulation which describes the MOSFET region from pinch-off to drain contact based on the surface potential. The model relates the surface-potential increase beyond the pinch-off point to the channel/drain junction profile by applying the Gauss law with the assumption that the lateral field is greater than the vertical one. Explicit equations for the lateral field and the pinch-off length are obtained, which take the potential increase in the drain overlap region into account. The model, as implemented into a circuit simulator, correctly reproduces measured channel conductance and overlap capacitance for 100 nm pocket-implant technologies as a function of bias condition and gate length.

The urgent tasks of MOSFET modeling for circuit simulation are easy adaptation to new physical phenomena arising for advancing technologies, and, of course, sufficient simulation accuracy. Approaches currently being pursued for developing such MOSFET models are summarized. Their capabilities for accomplishing these tasks as well as the important remaining problems are discussed. Main focus is given on the model HiSIM, the first commonly available model based on the drift-diffusion approximation developed for 0.10 µm MOSFET technology node.

We present an evaluation method for estimating the lower bound number of Monte Carlo STA trials required to obtain at least one sample which falls within top-k % of its parent population. The sample can be used to ensure that target designs are timing-error free with a predefined probability using the minimum computational cost. The lower bound number is represented as a closed-form formula which is general enough to be applied to other verifications. For validation, Monte Carlo STA was carried out on various benchmark data including ISCAS circuits. The minimum number of Monte Carlo runs determined using the proposed method successfully extracted one or more top-k % delay instances.