A scalable MOSFET parasitic model has been studied using 0.13 µm standard CMOS process. The model consisted of a core BSIM3v3 transistor model and parasitic resistor, capacitor, inductor, and diode. All parasitic components' values were automatically calculated by transistor geometrical parameters, only gate length (Lg), gate width (Wg), and gate multiple numbers (Mg), and some fixed process parameters such as sheet resistance of each part of diffusion layer. This model was confirmed for 0.25 µm to 0.5 µm gate length, 10 to 40 gate multiples with 5 µm gate finger width (Wf), 0.8 V to 1.5 V gate-source voltage (|Vgs|) with 0.6 V threshold voltage (|Vth|), and 1.0 V to 2.5 V drain-source voltage (|Vds|) from the viewpoint of small signal. The measured s-parameter and simulated one are in fairly good agreement in 200 MHz to 20 GHz frequencies range. This model is very simple, scalable, and convenient for RF circuit designers without difficult parameter setting.

In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H$_{2}$ annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50,nm fin width is satisfied with the requirement from 25,nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f$_{mathrm{T}}$ and f$_{mathrm{max}}$, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f$_{mathrm{T}}$ of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10,nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.

A systematic experimental and modeling study is reported, which characterizes the low-frequency noise spectrum of 100 nm-MOSFETs accurately. Two kinds of measured spectra are observed: 1/f and non-1/f spectra. The non-1/f spectrum is analysed by forward and backward measurements with exchanged source and drain, and shown to be due to a randomly distributed inhomogeneity of the trap density along the channel and within the gate oxide. By averaging the spectra of identical MOSFETs on a wafer the measured non-1/f noise spectra reduce to a 1/f characteristics. On the basis of these measurement data a noise model for circuit simulation is developed, which reproduces the low-frequency noise spectrum with a single model parameter for all gate lengths and under any bias conditions.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.