IEICE TRANSACTIONS on Fundamentals
Scalable Parasitic Components Model of CMOS for RF Circuit Design
Summary :
A scalable MOSFET parasitic model has been studied using 0.13 µm standard CMOS process. The model consisted of a core BSIM3v3 transistor model and parasitic resistor, capacitor, inductor, and diode. All parasitic components' values were automatically calculated by transistor geometrical parameters, only gate length (Lg), gate width (Wg), and gate multiple numbers (Mg), and some fixed process parameters such as sheet resistance of each part of diffusion layer. This model was confirmed for 0.25 µm to 0.5 µm gate length, 10 to 40 gate multiples with 5 µm gate finger width (Wf), 0.8 V to 1.5 V gate-source voltage (|Vgs|) with 0.6 V threshold voltage (|Vth|), and 1.0 V to 2.5 V drain-source voltage (|Vds|) from the viewpoint of small signal. The measured s-parameter and simulated one are in fairly good agreement in 200 MHz to 20 GHz frequencies range. This model is very simple, scalable, and convenient for RF circuit designers without difficult parameter setting.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.2 pp.288-298
- Publication Date
- 2003/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Nobuyuki ITOH
Tatsuya OHGURO
Kazuhiro KATOH
Hideki KIMIJIMA
Shin-ichiro ISHIZUKA
Kenji KOJIMA
Hiroyuki MIYAKAWA
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Nobuyuki ITOH, Tatsuya OHGURO, Kazuhiro KATOH, Hideki KIMIJIMA, Shin-ichiro ISHIZUKA, Kenji KOJIMA, Hiroyuki MIYAKAWA, "Scalable Parasitic Components Model of CMOS for RF Circuit Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 2, pp. 288-298, February 2003, doi: .
Abstract: A scalable MOSFET parasitic model has been studied using 0.13 µm standard CMOS process. The model consisted of a core BSIM3v3 transistor model and parasitic resistor, capacitor, inductor, and diode. All parasitic components' values were automatically calculated by transistor geometrical parameters, only gate length (Lg), gate width (Wg), and gate multiple numbers (Mg), and some fixed process parameters such as sheet resistance of each part of diffusion layer. This model was confirmed for 0.25 µm to 0.5 µm gate length, 10 to 40 gate multiples with 5 µm gate finger width (Wf), 0.8 V to 1.5 V gate-source voltage (|Vgs|) with 0.6 V threshold voltage (|Vth|), and 1.0 V to 2.5 V drain-source voltage (|Vds|) from the viewpoint of small signal. The measured s-parameter and simulated one are in fairly good agreement in 200 MHz to 20 GHz frequencies range. This model is very simple, scalable, and convenient for RF circuit designers without difficult parameter setting.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_2_288/_p
Copy
@ARTICLE{e86-a_2_288,
author={Nobuyuki ITOH, Tatsuya OHGURO, Kazuhiro KATOH, Hideki KIMIJIMA, Shin-ichiro ISHIZUKA, Kenji KOJIMA, Hiroyuki MIYAKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Scalable Parasitic Components Model of CMOS for RF Circuit Design},
year={2003},
volume={E86-A},
number={2},
pages={288-298},
abstract={A scalable MOSFET parasitic model has been studied using 0.13 µm standard CMOS process. The model consisted of a core BSIM3v3 transistor model and parasitic resistor, capacitor, inductor, and diode. All parasitic components' values were automatically calculated by transistor geometrical parameters, only gate length (Lg), gate width (Wg), and gate multiple numbers (Mg), and some fixed process parameters such as sheet resistance of each part of diffusion layer. This model was confirmed for 0.25 µm to 0.5 µm gate length, 10 to 40 gate multiples with 5 µm gate finger width (Wf), 0.8 V to 1.5 V gate-source voltage (|Vgs|) with 0.6 V threshold voltage (|Vth|), and 1.0 V to 2.5 V drain-source voltage (|Vds|) from the viewpoint of small signal. The measured s-parameter and simulated one are in fairly good agreement in 200 MHz to 20 GHz frequencies range. This model is very simple, scalable, and convenient for RF circuit designers without difficult parameter setting.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - Scalable Parasitic Components Model of CMOS for RF Circuit Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 288
EP - 298
AU - Nobuyuki ITOH
AU - Tatsuya OHGURO
AU - Kazuhiro KATOH
AU - Hideki KIMIJIMA
AU - Shin-ichiro ISHIZUKA
AU - Kenji KOJIMA
AU - Hiroyuki MIYAKAWA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2003
AB - A scalable MOSFET parasitic model has been studied using 0.13 µm standard CMOS process. The model consisted of a core BSIM3v3 transistor model and parasitic resistor, capacitor, inductor, and diode. All parasitic components' values were automatically calculated by transistor geometrical parameters, only gate length (Lg), gate width (Wg), and gate multiple numbers (Mg), and some fixed process parameters such as sheet resistance of each part of diffusion layer. This model was confirmed for 0.25 µm to 0.5 µm gate length, 10 to 40 gate multiples with 5 µm gate finger width (Wf), 0.8 V to 1.5 V gate-source voltage (|Vgs|) with 0.6 V threshold voltage (|Vth|), and 1.0 V to 2.5 V drain-source voltage (|Vds|) from the viewpoint of small signal. The measured s-parameter and simulated one are in fairly good agreement in 200 MHz to 20 GHz frequencies range. This model is very simple, scalable, and convenient for RF circuit designers without difficult parameter setting.
ER -
English
