A scalable MOSFET parasitic model has been studied using 0.13 µm standard CMOS process. The model consisted of a core BSIM3v3 transistor model and parasitic resistor, capacitor, inductor, and diode. All parasitic components' values were automatically calculated by transistor geometrical parameters, only gate length (Lg), gate width (Wg), and gate multiple numbers (Mg), and some fixed process parameters such as sheet resistance of each part of diffusion layer. This model was confirmed for 0.25 µm to 0.5 µm gate length, 10 to 40 gate multiples with 5 µm gate finger width (Wf), 0.8 V to 1.5 V gate-source voltage (|Vgs|) with 0.6 V threshold voltage (|Vth|), and 1.0 V to 2.5 V drain-source voltage (|Vds|) from the viewpoint of small signal. The measured s-parameter and simulated one are in fairly good agreement in 200 MHz to 20 GHz frequencies range. This model is very simple, scalable, and convenient for RF circuit designers without difficult parameter setting.

This paper describes a low-power-supply 2-GHz CMOS up-converter. A current-mode mixing method using current adding and self-switching mixers is proposed for 1-V operation. The current-mode up-converter achieves conversion gain of 6.7 dB and linearity of 6.5-dBm OIP3 at 1 V. Balanced configuration and DC offset canceller reduce LO leakage below -40 dBc even with 20-mV Vth mismatches. The bias circuit of the IC is designed to maintain constant conversion gain for variation of temperature for practical usage. The measurement results indicate the proposed up-converter is applicable for future wireless systems.