In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H$_{2}$ annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50,nm fin width is satisfied with the requirement from 25,nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f$_{mathrm{T}}$ and f$_{mathrm{max}}$, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f$_{mathrm{T}}$ of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10,nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.