Fluctuations of three device parameters (Tox, Nsub, ΔL) based on process fluctuations are taken as cause of device/circuit performances. In-line measured device parameters are approximated by Gaussian functions, and their 2σ values are assigned as boundaries of the performance fluctuations. Measured distributions both for device and curcuit performances are successfully reproduced.

A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

In this paper, we report the design of an organic thin-film transistor (OTFT) driver circuit for the actuator of an organic fluid pump, which can be integrated in a portable-size fully-organic artificial lung. Compared to traditional pump designs, lightness, compactness and scalability are achieved by adopting a creative pumping mechanism with a completely organic-material-based system concept. The transportable fluid volume is verified to be flexibly adjustable, enabling on-demand controllability and scalability of the pump's fluid-flow rate. The simulations, based on an accurate surface-potential OTFT compact model, demonstrate that the necessary driving waveforms can be efficiently generated and adjusted to the actuator requirements. At the actuator-driving-circuit frequency of 0.98Hz, an all-organic fluid pump with 40cm length and 0.2cm height is able to achieve a flow rate of 0.847L/min, which satisfies the requirements for artificial-lung assist systems to a weakened normal lung.

We have developed a new simulation methodology for predicting shot noise intensity in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). In our approach, shot noise in MOSFETs is calculated by employing a two dimensional device simulator in conjunction with the shot noise model of a p-n junction. The accuracy of the noise model has been demonstrated by comparing simulation results with measured noise data of p-n diodes. The intensity of shot noise in various n-MOSFET devices under various bias conditions was estimated beyond GHz operational frequency by using our simulation scheme. At DC or low-frequency region, sub-threshold current dominates the intensity of shot noise. Therefore, shot noise is independent on frequency in this region, and its intensity is exponentially depends on VG, proportional to L-1, and almost independent on VD. At high-frequency region above GHz frequency, on the other hand, shot noise intensity depends on frequency and is much larger than that of low-frequency region. In particular, the intensity of the RF shot noise is almost independent on L, VD and VG. This suggests that high-frequency shot noise intensity of MOSFETs is decided only by the conditions of source-bulk junction.

We have improved a compact model for the injection-enhancedinsulated-gate bipolar transistor for inverter circuit simulation. The holeaccumulation of floating-base region and potential change are modeled. It turned out that negative capacitance which occurs by floating-base region has the dependence of frequency. It is necessary to consider the frequency dependence of the total gate capacitance for transient simulation. We analyzed the relationship between negative gate capacitance and current rise rate at the switch turn-on timing and device structure. The development model simulation result is well reproduced $I_{ extrm{c}}$ and $V_{ extrm{ce}}$ of measurement data, and the switching loss calculation accuracy is improved.

The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

In LDMOS devices for high-voltage applications, there appears a notable fingerprint of current-voltage characteristics known as soft breakdown. Its mechanism is analyzed and modeled on LDMOS devices where a high resistive drift region exists. This analysis has revealed that the softness of breakdown, known as the expansion effect, withholding a run-away of current, is contributed by the flux of holes underneath the gate-overlap region originated by impact-ionization. The mechanism of the expansion effect is modeled and implemented into the compact model HiSIM_HV for circuit simulation. A good agreement between simulated characteristics and 2D-device simulation results is verified.

The long-standing problem of predicting circuit performance variations without a huge number of statistical investigations is demonstrated to be solvable by a surface-potential-based MOSFET model. Direct connection of model parameters to physical device parameters reflecting process variations and the reduced number of model parameters are the enabling key model properties. It has been proven that the surface-potential-based model HiSIM2 is capable of reproducing measured I-V and its derivatives' variations with those of device/process related model parameters. When used to predict 51-stage ring oscillator frequency variation including both inter- and intra-chip variation, it reproduces measurements with shortened simulation time.

Reverse-recovery modeling for p-i-n diodes in the high current-density conditions are discussed. With the dynamic carrier-distribution-based modeling approach, the reverse recovery behaviors are explained in the high current-density conditions, where the nonquasi-static (NQS) behavior of carriers in the drift region is considered. In addition, a specific feature under the high current-density condition is discussed. The proposed model is implemented into a commercial circuit simulator in the Verilog-A language and its reverse recovery modeling ability is verified with a two-dimensional (2D) device simulator, in comparison to the conventional lumped-charge modeling technique.

Circuit performance of SiC-MOSFET-based bidirectional isolated DC/DC converters is investigated based on circuit simulation with the physically accurate compact device model HiSIM_HV. It is demonstrated that the combined optimization of the MOSFETs Ron and of the inductances in the transformer can enable a conversion efficiency of more than 97%. The simulation study also verifies that the possible efficiency improvements are diminished due to the MOSFET-performance degradation, namely the carrier-mobility reduction, which results in a limitation of the possible Ron reduction. It is further demonstrated that an optimization of the MOSFET-operation conditions is important to utilize the resulting higher MOSFET performance for achieving additional converter efficiency improvements.

This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.

This work describes a new analytical MOSFET model for analog circuit simulation based on the charge-sheet model. The current equation consists of diffusion and drift components, therefore Ids is a smooth function of the applied voltages. Since the original charge-sheet model is valid only for long-channel transistors, it has been further developed to describe quarter-micron MOSFETs by introducing the lateral electric field Ey into the theory. The new model includes these field contributions self-consistently, and describes the drain current of MOSFETs from long to quarter-micron channel lengths with a single model parameter set without discontinuities in derivatives of the drain current Ids. The mobility reduction due to Ey is described by an empirical equation with physical parameter values taken from literature. Only two fitting parameters, the impurity scattering and the surface roughness scattering in the mobility equation, are added to the physical parameters. The subdiffusion lengths are also taken as fitting parameters. Though the new model reduces the number of fitting parameters totally to four, it reproduces measured Ids excellently for MOSFETs with all channel lengths. The model has been included in the parameter extraction program JANUS, which extracts model parameters automatically. The algorithm for parameter extraction is summarized.

The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.

We have developed a compact double-gate metal-oxide-semiconductor field-effect transistor model for circuit simulation considering the volume inversion effect by solving the Poisson equation explicitly. It is verified that applied voltage dependence of the calculated potential values both at the surface and at the center of the silicon layer reproduce 2 dimensional device simulation results for any device structure, confirming the validity of the model for device optimization.

We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90 nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.

A predictive compact model of p-MOSFET negative bias temperature instability (NBTI) degradation for circuit simulation is reported with unified description of the interface-state-generation and hole-trapping mechanisms. It is found that the hole-trapping is responsible for the initial stage of the stress degradation, and the interface-state generation dominates the degradation afterwards, especially under high stress conditions. The predictive compact model with 8 parameters enables to reproduce the measurement results of the NBTI degradation under a wide range of stress bias conditions. Finally, the developed NBTI model is implemented into the compact MOSFET model HiSIM for circuit degradation simiulation.

The major task in compact modeling for high power devices is to predict the switching waveform accurately because it determines the energy loss of circuits. Device capacitance mainly determines the switching characteristics, which makes accurate capacitance modeling inevitable. This paper presents a newly developed compact model HiSIM-GaN [Hiroshima University STARC IGFET Model for Gallium-Nitride-based High Electron Mobility Transistors (GaN-HEMTs)], where the focus is given on the accurate modeling of the field-plate (FP), which is introduced to delocalize the electric-field peak that occurs at the electrode edge. We demonstrate that the proposed model reproduces capacitance measurements of a GaN-HEMT accurately without fitting parameters. Furthermore, the influence of the field plate on the studied circuit performance is analyzed.

A systematic experimental and modeling study is reported, which characterizes the low-frequency noise spectrum of 100 nm-MOSFETs accurately. Two kinds of measured spectra are observed: 1/f and non-1/f spectra. The non-1/f spectrum is analysed by forward and backward measurements with exchanged source and drain, and shown to be due to a randomly distributed inhomogeneity of the trap density along the channel and within the gate oxide. By averaging the spectra of identical MOSFETs on a wafer the measured non-1/f noise spectra reduce to a 1/f characteristics. On the basis of these measurement data a noise model for circuit simulation is developed, which reproduces the low-frequency noise spectrum with a single model parameter for all gate lengths and under any bias conditions.