A predictive compact model of p-MOSFET negative bias temperature instability (NBTI) degradation for circuit simulation is reported with unified description of the interface-state-generation and hole-trapping mechanisms. It is found that the hole-trapping is responsible for the initial stage of the stress degradation, and the interface-state generation dominates the degradation afterwards, especially under high stress conditions. The predictive compact model with 8 parameters enables to reproduce the measurement results of the NBTI degradation under a wide range of stress bias conditions. Finally, the developed NBTI model is implemented into the compact MOSFET model HiSIM for circuit degradation simiulation.