This paper describes fully integrated active guard band filters for suppressing the substrate coupling noise and their noise suppression effect measured by test chip experiments. The noise cancellation circuit of the active guard band filters simply consists of an inverter and a source follower. The substrate noise suppression effect was measured by using a test chip fabricated in a 0.18 µm CMOS triple-well process for system-on-a-chip. The noise with the filter was less than 5% of that without the filter and the noise suppression effect was observed from 1 MHz to 200 MHz by the statistical measurement of the voltage comparator. The noise suppression effect was also observed for actual digital switching noise produced by digital inverters. Configuration of the active guard band filter was investigated by simulation and it is shown that high and uniform noise suppression effect is achieved by placing the guard bands in the L-shape around the target triple-well area on the p-substrate.

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.

A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.

Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-µA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.

A method called "active guard band filtering" is proposed for reducing substrate noise in analog and digital mixed-signal integrated circuits. A noise cancellation signal having an inverse value to the substrate noise is actively input into a guard band to suppress the substrate noise. An operational amplifier produces the noise cancellation signal based upon the substrate noise detected by one guard band and feeds this signal through another quard band into the substrate. This is done within the amplifier feedback loop, which includes the guard bands and the substrate. The noise suppression effect was measured by using 0.8µm CMOS test chip. Using active guard band filtering suppressed substrate noise to -40 dB of the original non-canceled noise level at 8 MHz. The noise suppression effect was also observed at frequencies up to 20MHz, with an external operational amplifier. The influence of parasitic impedance was found to be a key factor in noise suppression. An active guard band filter with an on-chip noise cancellation circuit will be even more effective for high frequencies, because it eliminates parasitic impedance due to external components.

We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90 nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.

This paper proposes a new architecture for multibit complex bandpass ΔΣAD modulators with built-in Switched-Capacitor (SC) circuits for application to Low-IF receivers such as used for Bluetooth and WLAN. In the realization of complex bandpass ΔΣAD modulators, we face the following problems: (i) SNR of AD converter is deteriorated by mismatches between internal analog I and Q paths. (ii) Layout design becomes complicated because of signal lines crossing by complex filter and feedback from DAC for I and Q paths in the complex modulator, and this increases required chip area. We propose a new structure for a complex bandpass ΔΣAD modulator which can be completely divided into two paths without layout crossing, and solves the problems mentioned above. The two parts of signal paths and circuits in the modulator are changed for I and Q while CLK is changed for High/Low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain timing, and they are switched by multiplexers to those used for Q and I paths at another timing. Therefore the influence from mismatches between I and Q paths is reduced by dynamic matching. As a result, the modulator is divided into two separate parts without crossing signal lines between I and Q paths and its layout design can be greatly simplified compared with conventional modulators. We have conducted MATLAB simulations to confirm the effectiveness of the proposed structure.

We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the ΔΣ modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two nine-level quantizers and four DACs are used in the modulator for low-power implementations and higher signal-to-noise-and-distortion (SNDR), but the nonlinearities of DACs are not noise-shaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18 µm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2. These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to low-IF receivers in wireless communication systems.

An AC coupling configuration for the active guard band filters is introduced for suppressing substrate coupling noise in analog and digital mixed-signal integrated circuits. With this method, a substrate-coupling-noise cancellation signal can be supplied to a ground-level substrate by using a single 3-V supply on-chip circuits. Noise was suppressed to a maximum of less than 0.05 from 100 Hz to 2 MHz in a 0.35-µm CMOS test chip. Both experiments and a simulation based on the substrate extraction model showed the similar dependence of the noise-suppression effect on the arrangement of the guard-bands and analog circuits. The simulation is thus effective for optimizing the arrangement to suppress noise effects when designing a chip.

Digital-switching noise coupled into sensitive analog circuits is a critical problem in large-scale integration of mixed analog and digital circuits. This paper describes noise coupling of this kind, especially, through the substrate in CMOS integrated circuits, and reviews recent technical solutions to this noise problem. Simplified models have been developed to simulate the substrate coupling rapidly and accurately. A method using a CMOS comparator was proposed for measuring the effects of substrate noise, and equivalent waveforms of actual substrate noise were obtained. A circuit tecnique, called active guard band filtering, that controls the noise source is a new approach to substrate noise decoupling. CAD methods for handling substrate-coupled switching noise are making design verification possible for practical mixed-signal LSIs.