IEICE TRANSACTIONS on Fundamentals
High-Speed Continuous-Time Subsampling Bandpass ΔΣ AD Modulator Architecture Employing Radio Frequency DAC
Summary :
This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.4 pp.916-923
- Publication Date
- 2006/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.4.916
- Type of Manuscript
- Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Category
Authors
Masafumi UEMORI
Haruo KOBAYASHI
Tomonari ICHIKAWA
Atsushi WADA
Koichiro MASHIKO
Toshiro TSUKADA
Masao HOTTA
Keyword
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Masafumi UEMORI, Haruo KOBAYASHI, Tomonari ICHIKAWA, Atsushi WADA, Koichiro MASHIKO, Toshiro TSUKADA, Masao HOTTA, "High-Speed Continuous-Time Subsampling Bandpass ΔΣ AD Modulator Architecture Employing Radio Frequency DAC" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 4, pp. 916-923, April 2006, doi: 10.1093/ietfec/e89-a.4.916.
Abstract: This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.4.916/_p
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@ARTICLE{e89-a_4_916,
author={Masafumi UEMORI, Haruo KOBAYASHI, Tomonari ICHIKAWA, Atsushi WADA, Koichiro MASHIKO, Toshiro TSUKADA, Masao HOTTA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Speed Continuous-Time Subsampling Bandpass ΔΣ AD Modulator Architecture Employing Radio Frequency DAC},
year={2006},
volume={E89-A},
number={4},
pages={916-923},
abstract={This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.},
keywords={},
doi={10.1093/ietfec/e89-a.4.916},
ISSN={1745-1337},
month={April},}
Copy
TY - JOUR
TI - High-Speed Continuous-Time Subsampling Bandpass ΔΣ AD Modulator Architecture Employing Radio Frequency DAC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 916
EP - 923
AU - Masafumi UEMORI
AU - Haruo KOBAYASHI
AU - Tomonari ICHIKAWA
AU - Atsushi WADA
AU - Koichiro MASHIKO
AU - Toshiro TSUKADA
AU - Masao HOTTA
PY - 2006
DO - 10.1093/ietfec/e89-a.4.916
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2006
AB - This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.
ER -
English
