This paper presents a high speed 64-b floating point (FP) multiplier that has a useful function for computer graphics(CG). The critical path delay is minimized by using high speed logic gates and limiting the stage number of series transmission gates (TG's). The high speed redundant binary architecture is applied to the multiplication of significands. This FP multiplier has a special function of "CG multiplication" that directly multiplies a pixel data by an FP data. This multiplier was fabricated by 0.5 µm CMOS technology with triple-level metal of interconnection. The active area size is 4.25.1mm2.The operating cycle time is 3.5 ns at the supply voltage of 3.3 V, which corresponds to the frequency of 286 MHz, Implementation of CG multiplication increases the transistor count only 4%. Also, CG multiplication has no effect on the delay in the critical path.

We present a 64-b adder having a 2.6-ns delay time at 3.3 V power supply within 0.27 mm2 using 0.5-µm CMOS technology. We derived our adder design from architectural level considerations. The considerations include not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. As a result, a 64-b adder, (56-b Carry Look-ahead Adder(CLA) +8-b Carry Select Adder (CSA)), was designed. In this design, a new carry select scheme called Modified Carry Select (MCS) is also proposed.

This paper proposes a new architecture for multibit complex bandpass ΔΣAD modulators with built-in Switched-Capacitor (SC) circuits for application to Low-IF receivers such as used for Bluetooth and WLAN. In the realization of complex bandpass ΔΣAD modulators, we face the following problems: (i) SNR of AD converter is deteriorated by mismatches between internal analog I and Q paths. (ii) Layout design becomes complicated because of signal lines crossing by complex filter and feedback from DAC for I and Q paths in the complex modulator, and this increases required chip area. We propose a new structure for a complex bandpass ΔΣAD modulator which can be completely divided into two paths without layout crossing, and solves the problems mentioned above. The two parts of signal paths and circuits in the modulator are changed for I and Q while CLK is changed for High/Low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain timing, and they are switched by multiplexers to those used for Q and I paths at another timing. Therefore the influence from mismatches between I and Q paths is reduced by dynamic matching. As a result, the modulator is divided into two separate parts without crossing signal lines between I and Q paths and its layout design can be greatly simplified compared with conventional modulators. We have conducted MATLAB simulations to confirm the effectiveness of the proposed structure.

Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.

This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).

We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the ΔΣ modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two nine-level quantizers and four DACs are used in the modulator for low-power implementations and higher signal-to-noise-and-distortion (SNDR), but the nonlinearities of DACs are not noise-shaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18 µm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20 MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm2. These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to low-IF receivers in wireless communication systems.

This paper proposes a dual port color palette SRAM using a single bit line cell. Since the single bit line cell consists of fewer bit lines and transistors than standard dual port cells, it is able to reduce the area. However, the cell has had a problem in writing a high level. The port swap architecture solves the problem without any special mechanism such as a boot strap. In the architecture, each of two bit lines is assigned to the read/write MPU port and the read only pixel port, respectively. When writing a low level, the MPU port uses pre-assigned bit line. On the other hand, when writing a high level, the MPU port uses the bit line assigned to the pixel port by a swap operation. During the swapping, the pixel port continues the read operation by using the bit line assigned to the MPU port. A color palette using this architecture is fabricated with a 0. 5 µm CMOS process technology. The memory cell size reduces by up to 43% compared with standard dual port cells. The color palette is able to supply the pixel data at 300 MHz at the supply voltage of 3.3 V. This speed is enough to support the practical highest resolution monitors in the world.

We propose a directly controlled emitter-follower circuit with a feedback type level stabilizer for low-voltage, low-power and high-speed bipolar ECL circuits. The emitter-follower circuit employs a current source structure that compensates speed and power for various supply voltage and temperature. The feedback controlled circuit with a small current source stabilizes 'High' level. At a power consumption of 1 mW/gate, the new circuit is 45% faster under the loaded condition (FO1, CL0.5 pF) and has 47% better load driving capability than conventional ECL gates.

Based on the partially-depleted, thin-film SOI/CMOS technology, the influence of reduced junction capacitance on the performance of the elementary gates and large scale gate array chip is reviewed. To further reduce the power consumption, SOI-specific device configurations, in which the body-bias is individually controlled, are effective in lowering the supply voltage and hence the power consumption while keeping the circuit speed. Two attempts are introduced: (1) DTMOS (Dynamic-Threshold MOS)/SOI to achieve ultra low-voltage and yet high-speed operation, and (2) ABB (Active-Body-Bias) MOS to enhance the current drive under the low supply voltage.

This paper discusses the features of SOI/CMOS circuits in comparison with bulk/CMOS circuits. We have to design circuits with small fan outs and short wires to take advantage of high-speed and low-power SOI/CMOS devices to their fullest. We can take advantage of the SOI/CMOS structure if the ratio of the source/drain capacitances to the gate capacitances is much greater in the load capacitance. Thus, we propose a new flip-flop circuit with a smaller gate capacitance. The flip-flop circuit operates 30% faster than the previous circuit at 2.0 V. We also propose a buffer circuit having less delay disparity between the complementary output signals. The buffer circuit has the delay disparity of 18 ps at 0.2 pF and 2.0 V. We fabricated an 8-bit frequency divider and a 4-bit demultiplexer using the proposed circuits and 0.35 µm SOI/CMOS process. The 8-bit frequency divider and the 4-bit demultiplexer operate at 2.8 GHz and 1.6 GHz, respectively, at 2.0 V.

This paper describes a 0.35µm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35µm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35µm 3.3 V bulk-CMOS gate array.

This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0), -1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant-binary addition/subtraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42. 1 ns with 0.35 µm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730µm 910 µm area.

A high-speed silicon-on-insulator (SOI) of a 1/8 frequency divider and a 64-bit adder were realized using an optimized gate-overlapped LDD and a self-aligned titanium silicide (TiSi2) source-drain structure. The advantages of the delay time and power consumption were analyzed by circuit simulation. The maximum operation frequency of the SOI divider is 2.9 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than the bulk-Si divider. The power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. On the other hand, the speed of the SOI adder is 1.9 nsec at 3.3 V. The SOI adder speed is about 1.3 times faster than the bulk adder. The power consumption of the SOI adder is about 80% of that of the bulk divider. It was found that the high speed, low power features of the SOI divider were due to the pass transistor which had low junction capacitance and little substrate bias effects, in addition to the low wiring capacitance and low fanout capacitance compared to the bulk adder. As a result, it is suggested that SOI circuits using pass transistor have a potential for GHz level systems and it is expected they will be applied to handy communication systems and portable computers used in the multimedia era.

This paper describes the design of a high-speed 4-2 compressor for fast multipliers. Through the survey of the six kinds of representative conventional 4-2 compressor (RBA 1-3 and NBA 1-3) in both the redundant binary (RB) and the normal binary (NB) scheme, we extracted two problems that degrades the operating speed. The first is the use of multi-input complex gates and the second is the existence of transmission gates (TG) at the input and/or output stages. To solve these problems, we propose high-speed 4-2 compressors using the RB scheme, which we call the high-speed redundant binary adders (HSRBAs). Six kinds of HSRBAs, HSRBA 1-6, were derived by making the Boolean equations suitable for high-speed CMOS circuits. Among them, HSRBA2, HSRBA4 and HSRBA6 have no multi-input complex gate and input/output TG, and perform at a delay time of 0.89 ns which is the fastest of all 4-2 compressors. We investigated the logical relation between HSRBAs and conventional 4-2 compressors by analyzing the Boolean equations for each circuit. This investigation shows that all the conventional redundant binary adders RBA1-3 have the same logic structures as HSRBA2. We also showed the conventional normal binary adders NBA1-3 have the same logic structures as HSRBA1, HSRBA3 and HSRBA5, respectively. This implies all 4-2 compressors can be derived from the same equation regardless of RB or NB. We applied the HSRBA2 to a 5454-bit multiplier using 0.5-µm CMOS technology. The multiplication time at the supply voltage of 3.3 V was 8.8 ns. This is the fastest 5454-bit multiplier with 0.5-µm CMOS so far, and 83% of the speed improvement is due to the high speed 4-2 compressor.

This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.