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Koichiro MASHIKO Kimio UEDA Tsutomu YOSHIMURA Takanori HIROTA Yoshiki WADA Jun TAKASOH Kazuo KUBO
Based on the partially-depleted, thin-film SOI/CMOS technology, the influence of reduced junction capacitance on the performance of the elementary gates and large scale gate array chip is reviewed. To further reduce the power consumption, SOI-specific device configurations, in which the body-bias is individually controlled, are effective in lowering the supply voltage and hence the power consumption while keeping the circuit speed. Two attempts are introduced: (1) DTMOS (Dynamic-Threshold MOS)/SOI to achieve ultra low-voltage and yet high-speed operation, and (2) ABB (Active-Body-Bias) MOS to enhance the current drive under the low supply voltage.
Tsutomu YOSHIMURA Kimio UEDA Jun TAKASOH Harufusa KONDOH
In this paper, we present a 10 Gbase Ethernet Transceiver that is suitable for 10 Gb/s Ethernet applications. The 10 Gbase Ethernet Transceiver LSI, which contains the high-speed interface and the fully integrated IEEE 802.3ae compliant logics, is fabricated in a 0.18 µm SOI/CMOS process and dissipates 2.9 W at 1.8 V supply. By incorporating the monolithic approach and the use of the advance CMOS process, this 10 GbE transceiver realizes a low power, low cost and compact solution for the exponentially increasing need of broadband network applications.