This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).

Even though BiCMOS process has an ability to make both BJT and MOSFET on single-chip, only BJT has been used for BiCMOS Si-MMIC LNA because of its low noise and high gain performance under low d. c. supply power. But the distortion performance of BJT should be improved for the receiver applications in some wireless systems. In this paper, intermodulation distortion characteristics comparison is carried out between BJT and MOSFET fabricated in the same BiCMOS process by the analysis based on the simplified transistor models with extracted device parameters. The analytical result shows that MOSFET has lower intermodulation distortion characteristics compared with BJT, and the result is evaluated by the measurements. In order to obtain both low distortion and low noise characteristics, a two-stage Si-MMIC LNA is developed by using BJT as the 1st stage and MOSFET as the 2nd stage of LNA. The fabricated LNA performs NF of 2.45 dB, gain of 19.3 dB, IIP3 of14.6 dBm and OIP3 of 4.7 dBm under 3 V/7.2 mA d. c. supply power.

For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.