Even though BiCMOS process has an ability to make both BJT and MOSFET on single-chip, only BJT has been used for BiCMOS Si-MMIC LNA because of its low noise and high gain performance under low d. c. supply power. But the distortion performance of BJT should be improved for the receiver applications in some wireless systems. In this paper, intermodulation distortion characteristics comparison is carried out between BJT and MOSFET fabricated in the same BiCMOS process by the analysis based on the simplified transistor models with extracted device parameters. The analytical result shows that MOSFET has lower intermodulation distortion characteristics compared with BJT, and the result is evaluated by the measurements. In order to obtain both low distortion and low noise characteristics, a two-stage Si-MMIC LNA is developed by using BJT as the 1st stage and MOSFET as the 2nd stage of LNA. The fabricated LNA performs NF of 2.45 dB, gain of 19.3 dB, IIP3 of14.6 dBm and OIP3 of 4.7 dBm under 3 V/7.2 mA d. c. supply power.

For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.

This paper describes a single-chip RF transce-iver LSI for 2.4-GHz-band Bluetooth applications. This chip uses a 0.5 µm BiCMOS process, which provides 23 GHz fT. The LSI consists of almost all the required RF and IF building blocks--a power amplifier (PA), a low noise amplifier (LNA), an image rejection mixer (IRM), channel-selection filters, a limiter, a received signal strength indicator (RSSI), a frequency discriminator, a voltage controlled oscillator (VCO), and a phase-locked loop (PLL) synthesizer. The transceiver consumes 34.4 mA in TX mode (PA, VCO, PLL) and 44.0 mA in RX mode (LNA, IRM, channel-selection filters, limiter, RSSI, frequency discriminator, VCO, PLL). Direct-up conversion with a frequency doubler is used for the TX architecture. In order to avoid the VCO pulling, we used a 1.2 GHz VCO with the frequency doubler. In the receiver section, a low-IF single conversion RX architecture is employed for the integration of the channel-selection filters. The transceiver has a proposed linear frequency discriminator with a wide input range. The wide input-frequency range discriminator is required to realize the lower IF RX architecture because of the higher ratio of frequency deviation to the center IF frequency. The discriminator is the delay line type, and consists of a mixer and a delay line circuit with a locked loop. The delay line connects to one input terminal of the mixer. By using the delay locked at one fourth of the period of the IF frequency, a quadrature phase shift IF signal is applied to the mixer input terminal. For the frequency discriminator, the DC output voltage changes in proportion to the input frequency and a wide input range is achieved. This RF transceiver sufficiently satisfies all the target specifications for short-range Bluetooth applications. By using this chip, a -80 dBm sensitivity is obtained for the 10-3 BER, and the transceiver can deliver an output power of over 0.0 dBm.

This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/D-As) suitable for 2.4-GHz and 5.2-GHz short-range wireless applications. The ICs are fabricated in a 0.18 µm bulk CMOS which has no extra processing steps for enhancing the RF performance. The successful use of the current-reuse topology and interdigitated capacitors (IDCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in the bulk CMOS leading to large RF substrate and conductor losses. The main measurement results of the two LN/D-As are as follows: a 3.8-dB noise figure (NF) and a 10.1-dB gain under the conditions of 1.8 V and 6 mA, a 3.4-dBm 1-dB gain compressed output power (P1dB) for a 2.4-V voltage supply and a 13-mA operating current for the 2.4-GHz LN/D-A, and a 4.9-dB NF and an 11.1-dB gain with a 1.8 V and 10 mA supply condition, a 2.3-dBm P1dB at 2.4 V and 16 mA for the 5.2-GHz LN/D-A. Both MMICs are suited for low-noise amplifiers and driver amplifiers in 2.4-GHz and 5.2-GHz low-cost, low-power wireless systems such as Bluetooth and hiperLAN.