IEICE TRANSACTIONS on Electronics
Si Substrate Resistivity Design for On-Chip Matching Circuit Based on Electro-Magnetic Simulation
Summary :
For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.7 pp.923-930
- Publication Date
- 2001/07/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Techniques for Constructing Microwave Simulators--Design and Analysis Tools for Electromagnetic Fields, Circuits, and Antennas--)
- Category
- Electromagnetics Simulation Techniques
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Masayoshi ONO, Noriharu SUEMATSU, Shunji KUBO, Kensuke NAKAJIMA, Yoshitada IYAMA, Tadashi TAKAGI, Osami ISHIDA, "Si Substrate Resistivity Design for On-Chip Matching Circuit Based on Electro-Magnetic Simulation" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 7, pp. 923-930, July 2001, doi: .
Abstract: For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_7_923/_p
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@ARTICLE{e84-c_7_923,
author={Masayoshi ONO, Noriharu SUEMATSU, Shunji KUBO, Kensuke NAKAJIMA, Yoshitada IYAMA, Tadashi TAKAGI, Osami ISHIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Si Substrate Resistivity Design for On-Chip Matching Circuit Based on Electro-Magnetic Simulation},
year={2001},
volume={E84-C},
number={7},
pages={923-930},
abstract={For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - Si Substrate Resistivity Design for On-Chip Matching Circuit Based on Electro-Magnetic Simulation
T2 - IEICE TRANSACTIONS on Electronics
SP - 923
EP - 930
AU - Masayoshi ONO
AU - Noriharu SUEMATSU
AU - Shunji KUBO
AU - Kensuke NAKAJIMA
AU - Yoshitada IYAMA
AU - Tadashi TAKAGI
AU - Osami ISHIDA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2001
AB - For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.
ER -
English
