A Single-Chip 2.4-GHz RF Transceiver LSI with a Wide-Input-Range Frequency Discriminator

Hiroshi KOMURASAKI; Hisayasu SATO; Masayoshi ONO; Ryoji HAYASHI; Takeo EBANA; Harunobu TAKEDA; Kohji TAKAHASHI; Yutaka HAYASHI; Tetsuya IGA; Kohichi HASEGAWA; Takahiro MIKI

A Single-Chip 2.4-GHz RF Transceiver LSI with a Wide-Input-Range Frequency Discriminator

Hiroshi KOMURASAKI, Hisayasu SATO, Masayoshi ONO, Ryoji HAYASHI, Takeo EBANA, Harunobu TAKEDA, Kohji TAKAHASHI, Yutaka HAYASHI, Tetsuya IGA, Kohichi HASEGAWA, Takahiro MIKI

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This paper describes a single-chip RF transce-iver LSI for 2.4-GHz-band Bluetooth applications. This chip uses a 0.5 µm BiCMOS process, which provides 23 GHz fT. The LSI consists of almost all the required RF and IF building blocks--a power amplifier (PA), a low noise amplifier (LNA), an image rejection mixer (IRM), channel-selection filters, a limiter, a received signal strength indicator (RSSI), a frequency discriminator, a voltage controlled oscillator (VCO), and a phase-locked loop (PLL) synthesizer. The transceiver consumes 34.4 mA in TX mode (PA, VCO, PLL) and 44.0 mA in RX mode (LNA, IRM, channel-selection filters, limiter, RSSI, frequency discriminator, VCO, PLL). Direct-up conversion with a frequency doubler is used for the TX architecture. In order to avoid the VCO pulling, we used a 1.2 GHz VCO with the frequency doubler. In the receiver section, a low-IF single conversion RX architecture is employed for the integration of the channel-selection filters. The transceiver has a proposed linear frequency discriminator with a wide input range. The wide input-frequency range discriminator is required to realize the lower IF RX architecture because of the higher ratio of frequency deviation to the center IF frequency. The discriminator is the delay line type, and consists of a mixer and a delay line circuit with a locked loop. The delay line connects to one input terminal of the mixer. By using the delay locked at one fourth of the period of the IF frequency, a quadrature phase shift IF signal is applied to the mixer input terminal. For the frequency discriminator, the DC output voltage changes in proportion to the input frequency and a wide input range is achieved. This RF transceiver sufficiently satisfies all the target specifications for short-range Bluetooth applications. By using this chip, a -80 dBm sensitivity is obtained for the 10^-3 BER, and the transceiver can deliver an output power of over 0.0 dBm.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.7 pp.1419-1427

Publication Date: 2002/07/01

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Type of Manuscript: Special Section PAPER (Special Issue on Silicon RF Device & Integrated Circuit Technologies)

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Hiroshi KOMURASAKI, Hisayasu SATO, Masayoshi ONO, Ryoji HAYASHI, Takeo EBANA, Harunobu TAKEDA, Kohji TAKAHASHI, Yutaka HAYASHI, Tetsuya IGA, Kohichi HASEGAWA, Takahiro MIKI, "A Single-Chip 2.4-GHz RF Transceiver LSI with a Wide-Input-Range Frequency Discriminator" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 7, pp. 1419-1427, July 2002, doi: .
Abstract: This paper describes a single-chip RF transce-iver LSI for 2.4-GHz-band Bluetooth applications. This chip uses a 0.5 µm BiCMOS process, which provides 23 GHz fT. The LSI consists of almost all the required RF and IF building blocks--a power amplifier (PA), a low noise amplifier (LNA), an image rejection mixer (IRM), channel-selection filters, a limiter, a received signal strength indicator (RSSI), a frequency discriminator, a voltage controlled oscillator (VCO), and a phase-locked loop (PLL) synthesizer. The transceiver consumes 34.4 mA in TX mode (PA, VCO, PLL) and 44.0 mA in RX mode (LNA, IRM, channel-selection filters, limiter, RSSI, frequency discriminator, VCO, PLL). Direct-up conversion with a frequency doubler is used for the TX architecture. In order to avoid the VCO pulling, we used a 1.2 GHz VCO with the frequency doubler. In the receiver section, a low-IF single conversion RX architecture is employed for the integration of the channel-selection filters. The transceiver has a proposed linear frequency discriminator with a wide input range. The wide input-frequency range discriminator is required to realize the lower IF RX architecture because of the higher ratio of frequency deviation to the center IF frequency. The discriminator is the delay line type, and consists of a mixer and a delay line circuit with a locked loop. The delay line connects to one input terminal of the mixer. By using the delay locked at one fourth of the period of the IF frequency, a quadrature phase shift IF signal is applied to the mixer input terminal. For the frequency discriminator, the DC output voltage changes in proportion to the input frequency and a wide input range is achieved. This RF transceiver sufficiently satisfies all the target specifications for short-range Bluetooth applications. By using this chip, a -80 dBm sensitivity is obtained for the 10^-3 BER, and the transceiver can deliver an output power of over 0.0 dBm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_7_1419/_p

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@ARTICLE{e85-c_7_1419,
author={Hiroshi KOMURASAKI, Hisayasu SATO, Masayoshi ONO, Ryoji HAYASHI, Takeo EBANA, Harunobu TAKEDA, Kohji TAKAHASHI, Yutaka HAYASHI, Tetsuya IGA, Kohichi HASEGAWA, Takahiro MIKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single-Chip 2.4-GHz RF Transceiver LSI with a Wide-Input-Range Frequency Discriminator},
year={2002},
volume={E85-C},
number={7},
pages={1419-1427},
abstract={This paper describes a single-chip RF transce-iver LSI for 2.4-GHz-band Bluetooth applications. This chip uses a 0.5 µm BiCMOS process, which provides 23 GHz fT. The LSI consists of almost all the required RF and IF building blocks--a power amplifier (PA), a low noise amplifier (LNA), an image rejection mixer (IRM), channel-selection filters, a limiter, a received signal strength indicator (RSSI), a frequency discriminator, a voltage controlled oscillator (VCO), and a phase-locked loop (PLL) synthesizer. The transceiver consumes 34.4 mA in TX mode (PA, VCO, PLL) and 44.0 mA in RX mode (LNA, IRM, channel-selection filters, limiter, RSSI, frequency discriminator, VCO, PLL). Direct-up conversion with a frequency doubler is used for the TX architecture. In order to avoid the VCO pulling, we used a 1.2 GHz VCO with the frequency doubler. In the receiver section, a low-IF single conversion RX architecture is employed for the integration of the channel-selection filters. The transceiver has a proposed linear frequency discriminator with a wide input range. The wide input-frequency range discriminator is required to realize the lower IF RX architecture because of the higher ratio of frequency deviation to the center IF frequency. The discriminator is the delay line type, and consists of a mixer and a delay line circuit with a locked loop. The delay line connects to one input terminal of the mixer. By using the delay locked at one fourth of the period of the IF frequency, a quadrature phase shift IF signal is applied to the mixer input terminal. For the frequency discriminator, the DC output voltage changes in proportion to the input frequency and a wide input range is achieved. This RF transceiver sufficiently satisfies all the target specifications for short-range Bluetooth applications. By using this chip, a -80 dBm sensitivity is obtained for the 10^-3 BER, and the transceiver can deliver an output power of over 0.0 dBm.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - A Single-Chip 2.4-GHz RF Transceiver LSI with a Wide-Input-Range Frequency Discriminator
T2 - IEICE TRANSACTIONS on Electronics
SP - 1419
EP - 1427
AU - Hiroshi KOMURASAKI
AU - Hisayasu SATO
AU - Masayoshi ONO
AU - Ryoji HAYASHI
AU - Takeo EBANA
AU - Harunobu TAKEDA
AU - Kohji TAKAHASHI
AU - Yutaka HAYASHI
AU - Tetsuya IGA
AU - Kohichi HASEGAWA
AU - Takahiro MIKI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2002
AB - This paper describes a single-chip RF transce-iver LSI for 2.4-GHz-band Bluetooth applications. This chip uses a 0.5 µm BiCMOS process, which provides 23 GHz fT. The LSI consists of almost all the required RF and IF building blocks--a power amplifier (PA), a low noise amplifier (LNA), an image rejection mixer (IRM), channel-selection filters, a limiter, a received signal strength indicator (RSSI), a frequency discriminator, a voltage controlled oscillator (VCO), and a phase-locked loop (PLL) synthesizer. The transceiver consumes 34.4 mA in TX mode (PA, VCO, PLL) and 44.0 mA in RX mode (LNA, IRM, channel-selection filters, limiter, RSSI, frequency discriminator, VCO, PLL). Direct-up conversion with a frequency doubler is used for the TX architecture. In order to avoid the VCO pulling, we used a 1.2 GHz VCO with the frequency doubler. In the receiver section, a low-IF single conversion RX architecture is employed for the integration of the channel-selection filters. The transceiver has a proposed linear frequency discriminator with a wide input range. The wide input-frequency range discriminator is required to realize the lower IF RX architecture because of the higher ratio of frequency deviation to the center IF frequency. The discriminator is the delay line type, and consists of a mixer and a delay line circuit with a locked loop. The delay line connects to one input terminal of the mixer. By using the delay locked at one fourth of the period of the IF frequency, a quadrature phase shift IF signal is applied to the mixer input terminal. For the frequency discriminator, the DC output voltage changes in proportion to the input frequency and a wide input range is achieved. This RF transceiver sufficiently satisfies all the target specifications for short-range Bluetooth applications. By using this chip, a -80 dBm sensitivity is obtained for the 10^-3 BER, and the transceiver can deliver an output power of over 0.0 dBm.
ER -