In this paper, a high-frequency resolution Digital Frequency Discriminator (DFD) IC using a Time to Digital Converter (TDC) and an edge counter for Instantaneous Frequency Measurement (IFM) is proposed. In the proposed DFD, the TDC measures the time of the maximum periods of divided RF short pulse signals, and the edge counter counts the maximum number of periods of the signal. By measuring the multiple periods with the TDC and the edge counter, the proposed DFD improves the frequency resolution compared with that of the measuring one period because it is proportional to reciprocal of the measurement time of TDC. The DFD was fabricated using 0.18-um SiGe-BiCMOS. Frequency accuracy below 0.39MHz and frequency precision below 1.58 MHz-RMS were achieved during 50 ns detection time in 0.3 GHz to 5.5 GHz band with the temperature range from -40 to 85 degrees.

An optical FM system using an optical FM LD (laser diode) and an optical frequency discriminator (OFD), in which a nonlinear compensation scheme based on the interaction between its nonlinearities can minimize intermodulation distortion. This paper theoretically investigates the minimization influence for 3rd plus 5th order intermodulation distortion power for an optical FM radio-on-fiber system. The carrier to noise-plus-distortion power ratio (CNDR) is theoretically analyzed in employing the OFD whose transmission characteristic is controlled by a phase shifter. The results show that the designed receiver can achieve higher CNDR in the application of multicarrier transmission.

This paper describes a single-chip RF transce-iver LSI for 2.4-GHz-band Bluetooth applications. This chip uses a 0.5 µm BiCMOS process, which provides 23 GHz fT. The LSI consists of almost all the required RF and IF building blocks--a power amplifier (PA), a low noise amplifier (LNA), an image rejection mixer (IRM), channel-selection filters, a limiter, a received signal strength indicator (RSSI), a frequency discriminator, a voltage controlled oscillator (VCO), and a phase-locked loop (PLL) synthesizer. The transceiver consumes 34.4 mA in TX mode (PA, VCO, PLL) and 44.0 mA in RX mode (LNA, IRM, channel-selection filters, limiter, RSSI, frequency discriminator, VCO, PLL). Direct-up conversion with a frequency doubler is used for the TX architecture. In order to avoid the VCO pulling, we used a 1.2 GHz VCO with the frequency doubler. In the receiver section, a low-IF single conversion RX architecture is employed for the integration of the channel-selection filters. The transceiver has a proposed linear frequency discriminator with a wide input range. The wide input-frequency range discriminator is required to realize the lower IF RX architecture because of the higher ratio of frequency deviation to the center IF frequency. The discriminator is the delay line type, and consists of a mixer and a delay line circuit with a locked loop. The delay line connects to one input terminal of the mixer. By using the delay locked at one fourth of the period of the IF frequency, a quadrature phase shift IF signal is applied to the mixer input terminal. For the frequency discriminator, the DC output voltage changes in proportion to the input frequency and a wide input range is achieved. This RF transceiver sufficiently satisfies all the target specifications for short-range Bluetooth applications. By using this chip, a -80 dBm sensitivity is obtained for the 10-3 BER, and the transceiver can deliver an output power of over 0.0 dBm.

This paper proposes a new AFC (automatic frequency control) circuit employing a double-product type frequency discriminator to enable fast acquisition in very-low CNR (carrier to noise power ratio) environments. The frequency step responses of the proposed AFC circuit are theoretically analyzed. In addition this paper evaluates the performance of the proposed AFC circuit by computer simulation in very-low CNR environments. The simulation results confirm that click noise at the frequency discriminator causes large frequency tracking error and that this error can be improved by increasing the delay time of the double-product type frequency discriminator. The frequency error can be also reduced by introducing the proposed frequency discriminator to modify the frequency error detection performance. The acquisition time of the proposed AFC circuit can be reduced by about 100 symbols compared to the conventional cross-product type AFC circuit.