This paper presents an even harmonic quadrature mixer (EH-QMIX) with a simple filter configuration and an integrated LTCC module including LNAs, band rejection filters (BRFs), and the proposed EH-QMIX for W-CDMA direct conversion receiver (DCR). Since the DCR has no spurious responses, a BRF instead of a high-Q band pass filter can be applicable for eliminating undesired signals and it can be built in the LTCC substrates easily. As LO frequency is half of RF frequency in the EH-QMIX, diplexer can be composed of simple filters and it can be also integrated in the substrates. As a result, the whole RF circuits of the EH-DCR using a proposed EH-QMIX are integrated in the LTCC module and miniaturization of the receiver is achieved. Moreover, in order to suppress the degradation of the amplitude and the phase imbalances in the quadrature mixer caused by interferences of signals, RF characteristics of the circuits in the mixer such as reflection coefficients, isolations are discussed. A developed LTCC module shows good performances for W-CDMA direct conversion receiver.

A novel common emitter common collector transistor pair (CECCTP) mixer is presented. A LO pumped CECCTP enables even harmonic mixing operation, and a balanced CECCTP mixer configuration enables the suppression of both 2fLO and fIM2 which are undesirable component for direct conversion mixer. A 2 GHz-band balanced CECCTP mixer is fabricated in SiGe HBT process, and the direct conversion characteristics are measured. It performs conversion gain of 8.8 dB, NF of 14.9 dB and IIP2 of 42.3 dBm when LO power is -6 dBm, supplied voltage is 3 V and current is 5 mA.

This paper presents an even harmonic mixer using self-biased anti-parallel diode pair (APDP). A proposed self-biased APDP is composed of a pair of diodes and self-bias series resistors. At high LO injection level, rectified current is generated by the diodes and reverse voltage is applied to the diodes by the self-bias resistor. Therefore, rapid degradation of conversion loss at high LO input level can be avoided. The effect of self-bias resistor is explained by using simplified behavior model and harmonic balance method, and is evaluated by the measurements of an L-band even harmonic type direct conversion mixer.

An adaptively phase-shift controlled self-injection locked VCO is described. A self-injection locking technique is effective to reduce phase noise. However, a conventional self-injection locked VCO has drawbacks of discontinuous frequency sweep which means narrow bandwidth, and large variation of phase noise. Our proposed adaptively phase-shift controlled self-injection locked VCO overcomes these drawbacks by detecting phase-shift of the self-injection feedback and controlling the phase-shift depending on sweep of the oscillation frequency. This paper describes analysis of relationships between the discontinuity and feedback phase-shift of the self-injection locked VCO. In addition, a VCO-IC which includes a Ka-band VCO and a phase detector is designed and fabricated in 0.18um SiGe BiCMOS technology. Measurement results of the proposed self-injection locked VCO using the fabricated IC show the improvement to the drawbacks. In the proposed self-injection locked VCO, the oscillation frequency sweep is continuous and the phase noise variation is less than 5 dB.

The average bit error rate performances of M-ary orthogonal code shift keying (CSK) in Rician fading environments are analyzed in this letter. CSK is a digital modulation scheme that uses a code set as M-ary signals. In CSK, one code is selected from a code set containing M codes according to the information data. A signal is modulated by using this code and the effect of fading can be reduced by applying interleaving to the elements of the codes. In the analysis, the bit error probability is derived in closed form expression by using the Chernoff bound. The analysis results show that the error probability decreases when the code length is increased and that an arbitrarily small error probability is achieved as the code length approaches infinity, provided that Eb/N0 exceeds 1.42 dB.

An ESL-cancelling circuit for a shunt-connected film capacitor filter using vertically stacked coupled square loops is reported in this paper. The circuit is applicable for a shunt-connected capacitor filter whose equivalent series inductance (ESL) of the shunt-path causes deterioration of filter performance at frequencies above the self-resonant frequency. Two pairs of vertically stacked magnetically coupled square loops are used in the circuit those can equivalently add negative inductance in series to the shunt-path to cancel ESL for improvement of the filter performance. The ESL-cancelling circuit for a 1-μF film capacitor was designed according to the Biot-Savart law and electromagnetic (EM)-analysis, and the prototype was fabricated with an FR4 substrate. The measured result showed 20-dB improvement of the filter performance above the self-resonant frequency as designed, satisfying Sdd21 less than -40dB at 1MHz to 100MHz. This result is almost equivalent to reduce ESL of the shunt-path to less than 1nH at 100MHz and is also difficult to realize using any kind of a single bulky film capacitor without cancelling ESL.

A 2 to 5 GHz-band self frequency dividing quadrature mixer utilizing current re-use configuration with small size and broad band operation is proposed for a direct conversion receiver and a low-IF receiver of cognitive radio. The proposed mixer operates at twice the LO frequency by directly using a static type flip-flop frequency divider as the LO switching circuit for quadrature signal generation. The current re-use configuration is realized because the dc current of the frequency divider and the RF common-emitter amplifier share the same current flow path. Simulations and experiments verify that the proposed mixer offers broad band operation, miniaturization, and low power consumption. The mixer IC fabricated by 0.35 µm SiGe-BiCMOS technology achieved the conversion gain of 20.6 dB, noise figure of 11.9 dB and EVM for π/4-shift QPSK signal of 4.4% at 2.1 GHz with power consumption of 15 mW and size of 0.22 0.31 mm2. For the confirmation of broad band operation, the characteristics of conversion gain and noise figure were measured at 5.2 GHz. The proposed mixer could operate at 5.2 GHz with enough conversion gain, but the noise figure was inferior to that of 2.1 GHz. Therefore the further investigation and improvement about the noise figure will be needed for higher frequency.

A 15GHz-band 4-channel transmit/receive RF core-chip is presented for high SHF wide-band massive MIMO in 5G. In order to realize small RF frontend for 5G base stations, both 6bit phase shifters (PS) and 0.25 dB resolution variable gain amplifiers (VGA) are integrated in TX and RX paths of 4-channels on the chip. A PS calibration technique is applied to compensate the error of 6bit PS caused by process variations. A common gate current steering topology with tail current control is used for VGA to enhance the gain control accuracy. The 15GHz-band RF core-chip fabricated in 65 nm CMOS process achieved phase control error of 1.9deg. rms., and amplitude control error of 0.23 dB. rms.

In this paper, a high-frequency resolution Digital Frequency Discriminator (DFD) IC using a Time to Digital Converter (TDC) and an edge counter for Instantaneous Frequency Measurement (IFM) is proposed. In the proposed DFD, the TDC measures the time of the maximum periods of divided RF short pulse signals, and the edge counter counts the maximum number of periods of the signal. By measuring the multiple periods with the TDC and the edge counter, the proposed DFD improves the frequency resolution compared with that of the measuring one period because it is proportional to reciprocal of the measurement time of TDC. The DFD was fabricated using 0.18-um SiGe-BiCMOS. Frequency accuracy below 0.39MHz and frequency precision below 1.58 MHz-RMS were achieved during 50 ns detection time in 0.3 GHz to 5.5 GHz band with the temperature range from -40 to 85 degrees.