In order to meet various requirements for the 5th generation mobile communication, a high SHF wideband massive-MIMO system has been widely studied which offers wide system bandwidth and high spectral efficiency. A hybrid beamforming configuration which combines analog beamforming by APAA (Active Phased Array Antenna) and digital MIMO signal processing is one of the promising approaches for reducing the complexity and power consumption of the high SHF wideband massive-MIMO system. In order to realize the hybrid beamforming configuration in high SHF band, small size, low power consumption and precise beam forming over the wide-band frequency range are strongly required for RF frontend which constitutes analog beam former. In this paper, a compact RF frontend module for high SHF wideband 5G small cell base station is proposed. This RF frontend module is prototyped. Various key components of the RF frontend module are fabricated in 15GHz band, and measured results show that high RF performances are able to meet the requirements of RF frontend.

In this paper, a high-frequency resolution Digital Frequency Discriminator (DFD) IC using a Time to Digital Converter (TDC) and an edge counter for Instantaneous Frequency Measurement (IFM) is proposed. In the proposed DFD, the TDC measures the time of the maximum periods of divided RF short pulse signals, and the edge counter counts the maximum number of periods of the signal. By measuring the multiple periods with the TDC and the edge counter, the proposed DFD improves the frequency resolution compared with that of the measuring one period because it is proportional to reciprocal of the measurement time of TDC. The DFD was fabricated using 0.18-um SiGe-BiCMOS. Frequency accuracy below 0.39MHz and frequency precision below 1.58 MHz-RMS were achieved during 50 ns detection time in 0.3 GHz to 5.5 GHz band with the temperature range from -40 to 85 degrees.

This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.