Parallel Dual Modulus Prescaler with a Step Size of 0.5

Hideyuki NAKAMIZO; Kenichi TAJIMA; Ryoji HAYASHI; Kenji KAWAKAMI; Toshiya UOZUMI

doi:10.1587/transele.E95.C.1189

Parallel Dual Modulus Prescaler with a Step Size of 0.5

Hideyuki NAKAMIZO, Kenichi TAJIMA, Ryoji HAYASHI, Kenji KAWAKAMI, Toshiya UOZUMI

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This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E95-C No.7 pp.1189-1194

Publication Date: 2012/07/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E95.C.1189

Type of Manuscript: Special Section PAPER (Special Section on Recent Trends of Microwave Systems and Their Fundamental Technologies)

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Hideyuki NAKAMIZO, Kenichi TAJIMA, Ryoji HAYASHI, Kenji KAWAKAMI, Toshiya UOZUMI, "Parallel Dual Modulus Prescaler with a Step Size of 0.5" in IEICE TRANSACTIONS on Electronics, vol. E95-C, no. 7, pp. 1189-1194, July 2012, doi: 10.1587/transele.E95.C.1189.
Abstract: This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1189/_p

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@ARTICLE{e95-c_7_1189,
author={Hideyuki NAKAMIZO, Kenichi TAJIMA, Ryoji HAYASHI, Kenji KAWAKAMI, Toshiya UOZUMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Parallel Dual Modulus Prescaler with a Step Size of 0.5},
year={2012},
volume={E95-C},
number={7},
pages={1189-1194},
abstract={This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.},
keywords={},
doi={10.1587/transele.E95.C.1189},
ISSN={1745-1353},
month={July},}

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TY - JOUR
TI - Parallel Dual Modulus Prescaler with a Step Size of 0.5
T2 - IEICE TRANSACTIONS on Electronics
SP - 1189
EP - 1194
AU - Hideyuki NAKAMIZO
AU - Kenichi TAJIMA
AU - Ryoji HAYASHI
AU - Kenji KAWAKAMI
AU - Toshiya UOZUMI
PY - 2012
DO - 10.1587/transele.E95.C.1189
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2012
AB - This paper shows a new pulse swallow programmable frequency divider with the division step size of 0.5. To realize the division step size of 0.5 by a conventional pulse swallow method, we propose a parallel dual modulus prescaler with the division ratio of P and P + 0.5. It consists of simple circuit elements and has an advantage over the conventional dual modulus prescaler with the division step size of 0.5 in high frequency operation. The proposed parallel dual modulus prescaler with the division ratio 8 and 8.5 is implemented in the 0.13-µm CMOS technology. The proposed architecture achieves 7 times higher frequency operation than the conventional one theoretically. It is verified the functions over 5 GHz.
ER -